ATMEGA8HVA-4TU Atmel, ATMEGA8HVA-4TU Datasheet - Page 92
ATMEGA8HVA-4TU
Manufacturer Part Number
ATMEGA8HVA-4TU
Description
MCU AVR 8K FLASH 4MHZ 28-TSOP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16HVA-4CKU.pdf
(196 pages)
Specifications of ATMEGA8HVA-4TU
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 9 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
28-TSOP
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17.10.5
17.10.6
92
ATmega8HVA/16HVA
OCRnB – Timer/Counter n Output Compare Register B
TIMSKn – Timer/Counter n Interrupt Mask Register
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNTnL in 8-bit mode and TCNTnH in 16-bit mode). A match can be used to
generate an Output Compare interrupt.
In 16-bit mode the OCRnB register contains the high byte of the 16-bit Output Compare Regis-
ter. To ensure that both the high and the low bytes are written simultaneously when the CPU
writes to these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See
isters in 16-bit Mode” on page
Note that the OCRnB is not writable in Input Capture mode.
• Bit 3 – ICIEn: Timer/Counter n Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter n Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 2 – OCIEnB: Timer/Counter n Output Compare Match B Interrupt Enable
When the OCIEnB bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCFnB bit is set in the
Timer/Counter n Interrupt Flag Register” on page
• Bit 1 – OCIEnA: Timer/Counter n Output Compare Match A Interrupt Enable
When the OCIEnA bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter n Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter n occurs, i.e., when the OCFnA bit is set in the
Timer/Counter n Interrupt Flag Register” on page
• Bit 0 – TOIEn: Timer/Counter n Overflow Interrupt Enable
When the TOIEn bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter n Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter n occurs, i.e., when the TOVn bit is set in the
n Interrupt Flag Register” on page
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See Section “12.” on page
R/W
7
0
7
R
0
-
R/W
R
6
0
6
0
-
86.
R/W
93.
52.) is executed when the ICFn flag, located in TIFRn, is set.
R
5
0
5
0
-
R/W
R
4
0
4
0
-
OCRnB[7:0]
93.
93.
ICIEn
R/W
R/W
3
0
3
0
OCIEnB
R/W
R/W
2
0
2
0
OCIEnA
R/W
R/W
1
0
”TIFRn – Timer/Counter
1
0
”Accessing Reg-
TOIEn
R/W
R
0
0
0
0
8024A–AVR–04/08
”TIFRn –
”TIFRn –
OCRnB
TIMSKn
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