ATMEGA8HVA-4TU Atmel, ATMEGA8HVA-4TU Datasheet - Page 17
ATMEGA8HVA-4TU
Manufacturer Part Number
ATMEGA8HVA-4TU
Description
MCU AVR 8K FLASH 4MHZ 28-TSOP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16HVA-4CKU.pdf
(196 pages)
Specifications of ATMEGA8HVA-4TU
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 9 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
28-TSOP
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8.3.1
8024A–AVR–04/08
Data Memory Access Times
the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
The lower 768 data memory locations address both the Register File, the I/O memory, Extended
I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the
next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the
next 512 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
the 512 bytes of internal data SRAM in the ATmega8HVA/16HVA are all accessible through all
these addressing modes. The Register File is described in
page
Figure 8-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
11.
Data Memory Map
160 Ext I/O Reg.
64 I/O Registers
Data Memory
Internal SRAM
32 Registers
(512 x 8)
0x02FF
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
CPU
cycles as described in
ATmega8HVA/16HVA
”General Purpose Register File” on
Figure
8-3.
17
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