AT89C5132-RORUL Atmel, AT89C5132-RORUL Datasheet - Page 89

• Manufacturer Part Number: AT89C5132-RORUL
• Description: MCU 8051 FLASH USB 80TQFP
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5132-RORUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
• Peripherals: I²S, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 16-12. Command Line Controller Block Diagram
16.5.1
4173E–USB–09/07
Command Transmitter
Command Transmitter
Command Receiver
TX Pointer
RX Pointer
MMCON0.4
MMCON0.5
CRPTR
CTPTR
To send a command to the card, the user must load the command index (1 byte) and argument
(4 Bytes) in the command transmit FIFO using the MMCMD register. Before starting transmis-
sion by setting and clearing the CMDEN bit in MMCON1 register, the user must first configure:
•
•
•
Figure 16-13 summarizes the command transmission flow.
As soon as command transmission is enabled, the CFLCK flag in MMSTA is set indicating that
write to the FIFO is locked. This mechanism is implemented to avoid command over-run.
The end of the command transmission is signalled by the EOCI flag in MMINT register becoming
set. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 96.
The end of the command transmission also resets the CFLCK flag.
The user may abort command loading by setting and clearing the CTPTR bit in MMCON0 regis-
ter which resets the write pointer to the transmit FIFO.
17-byte FIFO
5-byte FIFO
MMCMD
MMCMD
RESPEN bit in MMCON1 register to indicate whether a response is expected or not.
RFMT bit in MMCON0 register to indicate the response size expected.
CRCDIS bit in MMCON0 register to indicate whether the CRC7 included in the response will
be computed or not. In order to avoid CRC error, CRCDIS may be set for responses that do
not include CRC7.
MMSTA.0
CFLCK
Write
Read
MMCON1.0
Data Converter
CMDEN
Data Converter
RESPEN
MMCON1.1
// -> Serial
Serial -> //
Finished State Machine
Finished State Machine
RX COMMAND Line
TX COMMAND Line
MMCON0.1
RFMT
MMSTA.2
CRC7S
CRC7 and Format
MMCON0.0
Generator
CRCDIS
CRC7
Checker
RESPFS
MMSTA.1
MMINT.5
MMINT.6
EOCI
EORI
AT89C5132
MCMD
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