PIC18LF8620T-I/PT Microchip Technology, PIC18LF8620T-I/PT Datasheet - Page 202

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PIC18LF8620T-I/PT

Manufacturer Part Number
PIC18LF8620T-I/PT
Description
IC MCU FLASH 32KX16 LV 80-TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF8620T-I/PT

Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Core
PIC
Processor Series
PIC18LF
Data Bus Width
8 bit
Maximum Clock Frequency
40 MHz
Data Ram Size
3840 B
Data Rom Size
1024 B
On-chip Adc
16 bit
Number Of Programmable I/os
68
Number Of Timers
2 x 8 bit
Operating Supply Voltage
2 V to 5.5 V
Mounting Style
SMD/SMT
Height
1 mm
Interface Type
I2C, SPI, USART
Length
12 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V, 5.8 V
Supply Voltage (min)
3.9 V, 4.2 V
Width
12 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF8620T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F6520/8520/6620/8620/6720/8720
18.1
The BRG supports both the Asynchronous and
Synchronous modes of the USARTs. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free running 8-bit timer. In Asyn-
chronous mode, bit BRGH (TXSTAx<2>) also controls
the baud rate. In Synchronous mode, bit BRGH is
ignored. Table 18-1 shows the formula for computation
of the baud rate for different USART modes, which only
apply in Master mode (internal clock).
Given the desired baud rate and F
integer value for the SPBRGx register can be calcu-
lated using the formula in Table 18-1. From this, the
error in baud rate can be determined.
EXAMPLE 18-1:
TABLE 18-1:
TABLE 18-2:
DS39609B-page 200
TXSTAx
RCSTAx
SPBRGx Baud Rate Generator Register
Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
Note 1:
Legend: X = value in SPBRGx (0 to 255)
Desired Baud Rate
Solving for X:
Calculated Baud Rate
Error
Name
SYNC
0
1
USART Baud Rate Generator
(BRG)
X
X
X
Register names generically refer to both of the identically named registers for the two USART modules,
where ‘x’ indicates the particular module. Bit names and Reset values are identical between modules.
CSRC
SPEN
Bit 7
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
(Asynchronous) Baud Rate = F
(Synchronous) Baud Rate = F
CALCULATING BAUD RATE ERROR
Bit 6
RX9
TX9
= F
= ((F
= ((16000000/9600)/64) – 1
=
=
=
=
=
=
[25.042] = 25
16000000/(64 (25 + 1))
9615
(Calculated Baud Rate – Desired Baud Rate)
(9615 – 9600)/9600
0.16%
OSC
OSC
BRGH = 0 (Low Speed)
SREN
TXEN
Bit 5
/(64 (X + 1))
/Desired Baud Rate)/64 ) – 1
OSC
Desired Baud Rate
, the nearest
CREN
SYNC
Bit 4
ADDEN
OSC
OSC
Bit 3
/(64(X + 1))
/(4(X + 1))
BRGH
FERR
Bit 2
Example 18-1 shows the calculation of the baud rate
error for the following conditions:
• F
• Desired Baud Rate = 9600
• BRGH = 0
• SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the equation in Example 18-1 can reduce the
baud rate error in some cases.
Writing a new value to the SPBRGx register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
18.1.1
The data on the RXx pin (either RC7/RX1/DT1 or RG2/
RX2/DT2) is sampled three times by a majority detect
circuit to determine if a high or a low level is present at
the pin.
OSC
OERR
TRMT
Bit 1
= 16 MHz
SAMPLING
RX9D
TX9D
Bit 0
Baud Rate = F
BRGH = 1 (High Speed)
 2004 Microchip Technology Inc.
0000 -010
0000 000x
0000 0000
POR, BOR
Value on
N/A
OSC
/(16(X + 1))
0000 -010
0000 000x
0000 0000
Value on
all other
Resets

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