PIC18LF8620T-I/PT Microchip Technology, PIC18LF8620T-I/PT Datasheet - Page 270

• Manufacturer Part Number: PIC18LF8620T-I/PT
• Description: IC MCU FLASH 32KX16 LV 80-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8620T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Core: PIC
• Processor Series: PIC18LF
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 3840 B
• Data Rom Size: 1024 B
• On-chip Adc: 16 bit
• Number Of Programmable I/os: 68
• Number Of Timers: 2 x 8 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Mounting Style: SMD/SMT
• Height: 1 mm
• Interface Type: I2C, SPI, USART
• Length: 12 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V, 5.8 V
• Supply Voltage (min): 3.9 V, 4.2 V
• Width: 12 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6520/8520/6620/8620/6720/8720
BCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39609B-page 268
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG = 0xC7
FLAG_REG = 0x47
Q1
register ‘f’
Bit Clear f
[ label ] BCF
0
0
a
0
None
Bit ‘b’ in register ‘f’ is cleared. If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
1
1
BCF
Read
1001
Q2
f
b
[0,1]
f<b>
255
7
FLAG_REG,
bbba
Process
Data
Q3
f,b[,a]
ffff
7, 0
register ‘f’
Write
Q4
ffff
BN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Negative
If Negative
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Negative
[ label ] BN
-128
if Negative bit is ‘1’
(PC) + 2 + 2n
None
If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
Q2
‘n’
‘n’
=
=
=
=
=
 2004 Microchip Technology Inc.
n
address (HERE)
1;
address (Jump)
0;
address (HERE+2)
127
0110
operation
BN
Process
Process
Data
Data
n
No
Q3
Q3
PC
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn