AT91SAM9G20B-CFU Atmel, AT91SAM9G20B-CFU Datasheet - Page 16

• Manufacturer Part Number: AT91SAM9G20B-CFU
• Description: IC MCU ARM9 247-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G20B-CFU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, ISI, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 247-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 400 MHz
• Number Of Programmable I/os: 96
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9G20-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.2.1
7.2.2
16
AT91SAM9G20 Summary
Matrix Masters
Matrix Slaves
The Bus Matrix of the AT91SAM9G20 manages six Masters, which means that each master can
perform an access concurrently with others, according the slave it accesses is available.
Each Master has its own decoder that can be defined specifically for each master. In order to
simplify the addressing, all the masters have the same decodings.
Table 7-1.
Each Slave has its own arbiter, thus allowing to program a different arbitration per Slave.
Table 7-2.
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
• Burst Management
• One Address Decoder provided per Master
• Boot Mode Select
• Remap Command
• Allows Handling of Dynamic Exception Vectors
– Round-Robin Arbitration, either with no default master, last accessed default master
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
– Three different slaves may be assigned to each decoded memory area: one for
– Non-volatile Boot Memory can be internal or external
– Selection is made by BMS pin sampled at reset
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
or fixed default master
internal boot, one for external boot, one after remap
List of Bus Matrix Masters
List of Bus Matrix Slaves
ARM926
ARM926 Data
PDC
ISI Controller
Ethernet MAC
USB Host DMA
Internal SRAM0 16 KBytes
Internal SRAM1 16 KBytes
Internal ROM
USB Host User Interface
External Bus Interface
Internal Peripherals
™
Instruction
6384DS–ATARM–13-Jan-10