AT91SAM9G20B-CFU Atmel, AT91SAM9G20B-CFU Datasheet - Page 25

IC MCU ARM9 247-LFBGA

AT91SAM9G20B-CFU

Manufacturer Part Number
AT91SAM9G20B-CFU
Description
IC MCU ARM9 247-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM9G20B-CFU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, ISI, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
247-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI, TWI, UART
Maximum Clock Frequency
400 MHz
Number Of Programmable I/os
96
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9G20-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9G20B-CFU
Manufacturer:
Atmel
Quantity:
10 000
9.2
9.3
9.4
6384DS–ATARM–13-Jan-10
Reset Controller
Shutdown Controller
Clock Generator
• Based on two Power-on-Reset cell
• Status of the last reset
• Controls the internal resets and the NRST pin output
• Shutdown and Wake-Up logic
• Embeds a Low Power 32768 Hz Slow Clock Oscillator and a Low power RC oscillator
• Embeds the Main Oscillator
• Embeds 2 PLLs
selectable with OSCSEL signal
– one on VDDBU and one on VDDCORE
– Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software
– Allows shaping a reset signal for the external devices
– Software programmable assertion of the SHDWN pin
– Deassertion Programmable on a WKUP pin level change or on alarm
– Provides the permanent Slow Clock SLCK to the system
– Oscillator bypass feature
– Supports 3 to 20 MHz crystals
– The PLL A outputs 400-800 MHz clock
– The PLL B outputs 100 MHz clock
– Both integrate an input divider to increase output accuracy
– PLL A and PLL B embed their own filters
reset, user reset or watchdog reset
AT91SAM9G20 Summary
25

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