ATMEGA64L-8MU Atmel, ATMEGA64L-8MU Datasheet - Page 313

• Manufacturer Part Number: ATMEGA64L-8MU
• Description: IC AVR MCU 64K 8MHZ 3V 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64L-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: JTAG/SPI/TWI/USART
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: MLF EP
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Package: 64MLF EP
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PROG_ENABLE (0x4)
PROG_COMMANDS
(0x5)
PROG_PAGELOAD
(0x6)
PROG_PAGEREAD
(0x7)
2490Q–AVR–06/10
The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-
bit Programming Enable Register is selected as data register. The active states are the
following:
•
•
The AVR specific public JTAG instruction for entering programming commands via the JTAG
port. The 15-bit Programming Command Register is selected as data register. The active states
are the following:
•
•
•
•
The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port.
The 1024-bit Virtual Flash Page Load Register is selected as data register. This is a virtual scan
chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8-
bit. Unlike most JTAG instructions, the Update-DR state is not used to transfer data from the
Shift Register. The data are automatically transferred to the Flash page buffer byte-by-byte in
the Shift-DR state by an internal state machine. This is the only active state:
•
Note:
The AVR specific public JTAG instruction to read one full Flash data page via the JTAG port.
The 1032-bit Virtual Flash Page Read Register is selected as data register. This is a virtual scan
chain with length equal to the number of bits in one Flash page plus eight. Internally the Shift
Register is 8-bit. Unlike most JTAG instructions, the Capture-DR state is not used to transfer
data to the Shift Register. The data are automatically transferred from the Flash page buffer
byte-by-byte in the Shift-DR state by an internal state machine. This is the only active state:
•
Note:
Shift-DR: the Programming enable signature is shifted into the data register.
Update-DR: The programming enable signature is compared to the correct value, and
programming mode is entered if the signature is valid.
Capture-DR: The result of the previous command is loaded into the data register.
Shift-DR: The data register is shifted by the TCK input, shifting out the result of the previous
command and shifting in the new command.
Update-DR: The programming command is applied to the Flash inputs
Run-Test/Idle: One clock cycle is generated, executing the applied command (not always
required, see
Shift-DR: Flash page data are shifted in from TDI by the TCK input, and automatically
loaded into the Flash page one byte at a time.
Shift-DR: Flash data are automatically read one byte at a time and shifted out on TDO by the
TCK input. The TDI input is ignored.
The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first device in
JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise program-
ming algorithm must be used.
The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the first device in
JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise program-
ming algorithm must be used.
Table 130 on page
316).
ATmega64(L)
313