ATMEGA64L-8MU Atmel, ATMEGA64L-8MU Datasheet - Page 75

• Manufacturer Part Number: ATMEGA64L-8MU
• Description: IC AVR MCU 64K 8MHZ 3V 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64L-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: JTAG/SPI/TWI/USART
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: MLF EP
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Package: 64MLF EP
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ATmega64(L)
• OC1B, Bit 6
OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the
Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one))
to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.
• OC1A, Bit 5
OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the
Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one))
to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.
• OC0, Bit 4
OC0, Output Compare Match output: The PB4 pin can serve as an external output for the
Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB4 set (one)) to
serve this function. The OC0 pin is also the output pin for the PWM mode timer function.
• MISO – Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a
Master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is
enabled as a Slave, the data direction of this pin is controlled by DDB3. When the pin is forced to
be an input, the pull-up can still be controlled by the PORTB3 bit.
• MOSI – Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a
Slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is
enabled as a Master, the data direction of this pin is controlled by DDB2. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB2 bit.
• SCK – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a
Slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is
enabled as a Master, the data direction of this pin is controlled by DDB1. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB1 bit.
• SS – Port B, Bit 0
SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an
input regardless of the setting of DDB0. As a Slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.
Table 31
and
Table 32
relate the alternate functions of Port B to the overriding signals shown in
Figure 33 on page
71. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal,
while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
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