ATMEGA64L-8MU Atmel, ATMEGA64L-8MU Datasheet - Page 320
ATMEGA64L-8MU
Manufacturer Part Number
ATMEGA64L-8MU
Description
IC AVR MCU 64K 8MHZ 3V 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64L-8MU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
JTAG/SPI/TWI/USART
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
MLF EP
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Package
64MLF EP
Family Name
ATmega
Maximum Speed
8 MHz
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
8MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA64L-8MUR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Virtual Flash Page
Load Register
Virtual Flash Page
Read Register
2490Q–AVR–06/10
The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of
bits in one Flash page. Internally the Shift Register is 8-bit, and the data are automatically trans-
ferred to the Flash page buffer byte-by-byte. Shift in all instruction words in the page, starting
with the LSB of the first instruction in the page and ending with the MSB of the last instruction in
the page. This provides an efficient way to load the entire Flash page buffer before executing
Page Write.
Figure 153. Virtual Flash Page Load Register
The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of
bits in one Flash page plus eight. Internally the Shift Register is 8-bit, and the data are automati-
cally transferred from the Flash data page byte-by-byte. The first eight cycles are used to
transfer the first byte to the internal Shift Register, and the bits that are shifted out during these
eight cycles should be ignored. Following this initialization, data are shifted out starting with the
LSB of the first instruction in the page and ending with the MSB of the last instruction in the
page. This provides an efficient way to read one full Flash page to verify programming.
TDO
TDI
D
A
T
A
Machine
State
STROBES
ADDRESS
EEPROM
Lock Bits
Fuses
Flash
ATmega64(L)
320
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