EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 145

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

DS785UM1
Note: The value in the register is the actual coefficient minus one.
Note: The value in the register is the actual coefficient minus one.
Note: This means that PLL1 FOUT is programmed to be 36,864,000 Hz on startup.
Note: The value in the register is the actual coefficient minus one.
Note: Care must be taken to make the correct selection of PCLK divide for the HCLK frequency
used, so that the required minimum ratio between PCLK and the peripheral clock is not
violated
PLL1_X2FBD2:
PLL1_X1FBD1:
PLL1_PS:
PCLKDIV:
HCLKDIV:
Copyright 2007 Cirrus Logic
These 6 register bits set the first feedback divider bits for
PLL1. On power-on-reset the value is set to 000111b (7
decimal).
These 5 register bits set the second feedback divider bits
for PLL1. On power-on-reset the value is set to 10011b (19
decimal).
These two bits determine the final divide on the VCO clock
signal in PLL1.
00 - Divide by 1
01 - Divide by 2
10 - Divide by 4
11 - Divide by 8
On power-on-reset these bits are reset to 11b (3 decimal).
These two bits set the divide ratio between the HCLK AHB
clock and the APB clock (PCLK)
00 - Divide by 1
01 - Divide by 2
10 - Divide by 4
11 - Divide by 8
On power-on-reset the value is set to 00b.
These three bits set the divide ratio between the VCO
output and the bus clock (HCLK)
000 - Divide by 1
001 - Divide by 2
010 - Divide by 4
011 - Divide by 5
On power-on-reset the value is set to 000b.
100 - Divide by 6
101 - Divide by 8
110 - Divide by 16
111 - Divide by 32
EP93xx User’s Guide
System Controller
5-19
5