EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 682
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
Available stocks
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Part Number
Manufacturer
Quantity
Price
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21
I
I2STXClkCfg
21-26
2
I
EP93xx User’s Guide
2
S Configuration and Status Register Descriptions
S Controller
31
15
Address:
Default
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x8082_0000 - Read/Write
0x0000_0000
Transmitter clock configuration register.
RSVD:
i2s_tx_bcr:
i2s_tx_nbcg:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Defines the TX bit clock rate.
00 - I2STXClkCfg[4] defines the bit clock generation.
01 - Bit clock rate is fixed at 32x. Word length is ignored.
10 - Bit clock rate is fixed at 64x. Word length is ignored.
11 - Bit clock rate is fixed at 128x. Word length is ignored.
Defines TX not bit clock gating mode.
If I2STXClkCfg[5:6] = 00, this bit defines the bit clock rate,
otherwise ignored.
Bit clock rate = 32x if word length is 16.
Bit clock rate = 64x if word length is 32.
Bit clock rate = 64x if word length is 24.
There is a special case when the word length is 24.
If this bit = 0 and the word length is 24, the last 8 cycles
are gated off in each word.
If this bit = 1 and the word length is 24, the last 8 cycles
are not gated off in each word.
24
8
RSVD
23
7
22
6
i2s_tx_bcr
21
5
i2s_tx_nbcg
20
4
i2s_mstr
19
3
i2s_trel
18
2
i2s_tckp
17
1
DS785UM1
i2s_tlrs
16
0
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