EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 5
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5. System Controller ............................................................................... 5-1
Chapter 6. Vectored Interrupt Controller............................................................. 6-1
Chapter 7. Raster Engine With Analog/LCD Integrated
DS785UM1
Timing and Interface ............................................................................................ 7-1
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
6.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
7.3 Raster Engine Features Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
7.4 Functional Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7
4.2.5 Synchronous Memory Operation.....................................................................................4-7
5.1.1 System Startup ................................................................................................................5-1
5.1.2 System Reset ..................................................................................................................5-1
5.1.3 Hardware Configuration Control ......................................................................................5-2
5.1.4 Software System Configuration Options..........................................................................5-4
5.1.5 Clock Control ...................................................................................................................5-4
5.1.6 Power Management ........................................................................................................5-9
5.1.7 Interrupt Generation ......................................................................................................5-12
6.1.1 Interrupt Priority ...............................................................................................................6-2
6.1.2 Interrupt Configuration.....................................................................................................6-3
6.1.3 Interrupt Details ...............................................................................................................6-4
7.3.1 Hardware Blinking ...........................................................................................................7-3
7.3.2 Color Look-Up Tables......................................................................................................7-4
7.3.3 Grayscale/Color Generation for Monochrome/Passive Low Color Displays ...................7-4
7.3.4 Frame Buffer Organization ..............................................................................................7-4
7.3.5 Frame Buffer Memory Size..............................................................................................7-6
7.3.6 Pulse Width Modulated Brightness..................................................................................7-6
7.3.7 Hardware Cursor .............................................................................................................7-7
7.4.1 VILOSATI (Video Image Line Output Scanner and Transfer Interface) ..........................7-8
7.4.2 Video FIFO ......................................................................................................................7-9
7.4.3 Video Pixel MUX............................................................................................................7-10
7.4.4 Blink Function ................................................................................................................7-10
7.4.5 Color Look-Up-Tables ...................................................................................................7-11
7.4.6 Color RGB Mux .............................................................................................................7-11
7.4.7 Pixel Shift Logic .............................................................................................................7-12
7.4.8 Grayscale/Color Generator for Monochrome/Passive Low Color Displays ...................7-15
5.1.5.1 Oscillators and Programmable PLLs .............................................................5-4
5.1.5.2 Bus and Peripheral Clock Generation ...........................................................5-5
5.1.5.3 Steps for Clock Configuration ........................................................................5-9
5.1.6.1 Clock Gatings ................................................................................................5-9
5.1.6.2 System Power States ..................................................................................5-10
7.4.8.1 HORZ_CNT3, HORZ_CNT4 Counters ........................................................7-16
7.4.8.2 VERT_CNT3, VERT_CNT4 Counters .........................................................7-16
7.4.8.3 FRAME_CNT3, FRAME_CNT4 Counters ...................................................7-16
7.4.8.4 HORZ_CNTx (pixel) timing ..........................................................................7-16
7.4.8.5 VERT_CNTx (line) timing ............................................................................7-16
©
Copyright 2007 Cirrus Logic, Inc.
EP93xx User’s Guide
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