EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 167
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
Available stocks
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Part Number
Manufacturer
Quantity
Price
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DS785UM1
TC1UI
TC2UI
AACINTR
DMAM2P0
DMAM2P1
DMAM2P2
DMAM2P3
DMAM2P4
DMAM2P5
DMAM2P6
DMAM2P7
DMAM2P8
DMAM2P9
DMAM2M0
DMAM2M1
UART1RXINTR1 UART 1 Receive Interrupt. See
Copyright 2007 Cirrus Logic
Timer Counter 1 Under Flow Interrupt. When Timer
Counter 1 has underflowed (reached zero), this interrupt
becomes active on the next falling edge of the timer’s
clock. The interrupt is cleared by writing any value to the
“Timer1Clear,”
Timer Counter 2 Under Flow Interrupt. When Timer
Counter 2 has underflowed (reached zero), this interrupt
becomes active on the next falling edge of the timer’s
clock. The interrupt is cleared by writing any value to the
“Timer2Clear,”
Advanced Audio CODEC Interrupt. See
"AC’97
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 0 Interrupt. See
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 1 Interrupt. See
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 2 Interrupt. See
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 3 Interrupt. See
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 4 Interrupt. See
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 5 Interrupt. See
Internal Memory-to-peripheral and Peripheral-to-memory
Channel 6 Interrupt. See
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 7 Interrupt. See
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 8 Interrupt. See
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 9 Interrupt. See
Memory-to-Memory (incorporating external M2P/P2M)
Channel 0 Interrupt. See
Memory-to-Memory (incorporating external M2P/P2M)
Channel 1 Interrupt. See
HDLC and Modem Control Signals"
Controller".
register. See
register. See
Chapter
Chapter
Chapter
Chapter
Chapter
Chapter
Chapter
Chapter
Chapter
Chapter
Chapter
Chapter
Chapter
Chapter
Chapter 14, "UART1 With
Vectored Interrupt Controller
10,
10,
10,
10,
10,
10,
10,
10,
10,
10,
10,
10,
18, "Timers".
18, "Timers".
"DMA
"DMA
"DMA
"DMA
"DMA
"DMA
"DMA
"DMA
"DMA
"DMA
"DMA
"DMA
EP93xx User’s Guide
Chapter
Controller".
Controller".
Controller".
Controller".
Controller".
Controller".
Controller".
Controller".
Controller".
Controller".
Controller".
Controller".
22,
6-5
6
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