EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 490

IC ARM920T MCU 200MHZ 352-PBGA

EP9312-IB

Manufacturer Part Number
EP9312-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9312-IB

Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1259

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12
12-12
Static Memory Controller
EP93xx User’s Guide
WPERR:
WP:
PME:
MW:
Copyright 2007 Cirrus Logic
The number of wait cycles for each of the 2nd, 3rd, and
4th accesses is specified by (WST2 + 1) HCLKs. For
example, if WST2 = 0x4, 4 + 1 = 5 cycles of HCLK are
inserted into the timing for each of the 2nd, 3rd, and 4th
accesses.
On reset, this field defaults to 0x1F (slowest access) to
enable booting from ROM or FLASH memory device
types.
Write Protect Error status flag - Read/Write
0 - No Error
1 - Write Protect Error
Writing a ‘1’ to this bit will clear the Write Protect status
error.
Write Protect - Read/Write
The value written to this bit specifies that either Writes to
the memory device are allowed to occur, or not occur:
0 - Yes (SRAM, FLASH)
1 - No (ROM, SRAM, FLASH)
Page Mode (Burst-of-4) Enable - Read/Write
0 - Page Mode is disabled, non-burst accesses occur
1 - Page Mode is enabled. Page Mode provides fast burst-
of-four accesses where the A[3] and A[4] address bits are
internally incremented, ‘00’ –> ‘01’ –> ‘10’ –> ‘11’, to
access four sequential words.
This bit is reset to ‘0’
Memory Width - Read/Write
The value written to this field specifies the bus-width of the
memory:
00 - 8-bit
01 - 16-bit
10 - 32-bit
11 - 32-bit
To support various bus-width memory devices for booting,
the MW field of the
automatically configured with the input values on the nCS7
and nCS6 pins, respectively. This takes place following a
power-on reset, but only if the input values on these pins
are: ASDO = ‘0’, Boot[1:0] = ‘00’, EEDAT = ‘1’. and EECLK
= ‘0’.
"SMCBCR[7:0]"
register can be
DS785UM1

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