EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 715

• Manufacturer Part Number: EP9312-IB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1259

DS785UM1
23.5.2 Master/Slave Mode
23.5.3 Serial Bit Rate Generation
23.5.4 Frame Format
To configure the SSP as a master, clear the SSPCR1 register master or slave selection bit
(MS) to 0, which is the default value on reset. Setting the SSPCR1 register MS bit to 1
configures the SSP as a slave. When configured as a slave, enabling or disabling of the SSP
SSPTXD signal is provided through the SSPCR1 slave mode SSPTXD output disable bit
(SOD).
The serial bit rate is derived by dividing down the 7.4 MHz SSPCLK. The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in SSPCPSR. The
clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value
programmed in SSPCR0. The frequency of the output signal bit clock, SCLKOUT, is defined
below:
Each data frame is between 4 and 16 bits long depending on the size of data programmed,
and is transmitted starting with the MSB. There are three basic frame types that can be
selected:
For all three formats, the serial clock (SCLKOUT) is held inactive while the SSP is idle, and
transitions at the programmed frequency only during active transmission or reception of data.
The idle state of SCLKOUT is utilized to provide a receive timeout indication that occurs
when the receive FIFO still contains data after a timeout period.
For Motorola SPI and National Semiconductor Microwire frame formats, the serial frame
(SFRMOUT) pin is active LOW, and is asserted (pulled down) during the entire transmission
of the frame.
For Texas Instruments synchronous serial frame format, the SFRMOUT pin is pulsed for one
serial clock period starting at its rising edge, prior to the transmission of each frame. For this
frame format, both the SSP and the off-chip slave device drive their output data on the rising
edge of SCLKOUT, and latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the National
Semiconductor Microwire format uses a special master-slave messaging technique, which
operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is
transmitted to the off-chip slave. During this transmit, no incoming data is received by the
SSP. After the message has been sent, the off-chip slave decodes it and, after waiting one
serial clock after the last bit of the 8-bit control message has been sent, responds with the
requested data. The returned data can be 4 to 16 bits in length, making the total frame length
anywhere from 13 to 25 bits.
• Texas Instruments synchronous serial
• Motorola SPI
• National Semiconductor Microwire.
Copyright 2007 Cirrus Logic
F
sspclkout
= F
sspclk
/ (cpsdvr
(1 + scr))
Synchronous Serial Port
EP93xx User’s Guide
23-3
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