ST72F324J4B6 STMicroelectronics, ST72F324J4B6 Datasheet - Page 98

• Manufacturer Part Number: ST72F324J4B6
• Description: IC MCU 8BIT 16K FLASH 42-PDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324J4B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST72324Jx ST72324Kx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.9 Clock Deviation Causes
The causes which contribute to the total deviation
are:
All the deviations of the system should be added
and compared to the SCI clock tolerance:
D
Figure 56. Bit Sampling in Reception Mode
98/164
1
RDI LINE
TRA
– D
– D
– D
– D
Sample
clock
oscillator error of the transmitter or the trans-
mitter is transmitting at a different baud rate).
tion of the receiver.
receiver: This deviation can occur during the
reception of one complete SCI message as-
suming that the deviation has been compen-
sated at the beginning of the message.
(generally due to the transceivers)
+ D
TRA
QUANT
REC
TCL
: Deviation due to the transmission line
QUANT
: Deviation due to transmitter error (Local
: Deviation of the local oscillator of the
: Error due to the baud rate quantiza-
+ D
1
REC
2
+ D
TCL
3
< 3.75%
7/16
4
5
6
One bit time
7
sampled values
10.5.4.10 Noise Error Causes
See also description of Noise error in
0.1.4.3
Start bit
The noise flag (NF) is set during start bit reception
if one of the following conditions occurs:
1. A valid falling edge is not detected. A falling
2. During sampling of the 16 samples, if one of the
Therefore, a valid Start Bit must satisfy both the
above conditions to prevent the Noise Flag getting
set.
Data Bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise
Flag getting set.
8
samples numbered 8, 9 and10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
edge is considered to be valid if the 3 consecu-
tive samples before the falling edge occurs are
detected as '1' and, after the falling edge
occurs, during the sampling of the 16 samples,
if one of the samples numbered 3, 5 or 7 is
detected as a “1”.
samples numbered 8, 9 or 10 is detected as a
“1”.
9
.
10
11
12
6/16
7/16
13
14
15
16
Section