EZ80F92AZ020EC00TR Zilog, EZ80F92AZ020EC00TR Datasheet - Page 116
EZ80F92AZ020EC00TR
Manufacturer Part Number
EZ80F92AZ020EC00TR
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F92AZ020EC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
EZ80F92AZ020EC00T
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eZ80F92/eZ80F93
Product Specification
109
then can discard the byte or take other appropriate action. If the interrupt is caused by a
receive-data-ready condition, the application alternately reads the UARTx_LSR and
UARTx_RBR registers and removes all of the received data bytes. It reads the
UARTx_LSR register before reading the UARTx_RBR register to determine that there is
no error in the received data.
To control and check modem status, the application sets up the modem by writing to the
UARTx_MCTL register and reading the UARTx_MSR register before starting the process
mentioned above.
When interrupts are disabled, all data transfers are referred to as
Poll Mode Transfers.
poll mode transfers. In poll mode transfers, the application must continually poll the
UARTx_LSR register to transmit or receive data without enabling the interrupts. The
same is true for the UARTx_MSR register. If the interrupts are not enabled, the data in the
UARTx_IIR register cannot be used to determine the cause of an interrupt.
Baud Rate Generator
The Baud Rate Generator consists of a 16-bit downcounter, two registers, and associated
decoding logic. The initial value of the Baud Rate Generator is defined by the two BRG
Divisor Latch registers, {UARTx_BRG_H, UARTx_BRG_L}. At the rising edge of each
system clock, the BRG decrements until it reaches the value
. On the next system
0001h
clock rising edge, the BRG reloads the initial value from {UARTx_BRG_H,
UARTx_BRG_L) and outputs a pulse to indicate the end-of-count. Calculate the UART
data rate with the following equation:
System Clock Frequency
UART Data Rate (bps)
=
16 X (UART Baud Rate Generator
Divisor)
Upon RESET, the 16-bit BRG divisor value resets to
. A minimum BRG divisor
0002h
value of
is also valid, and effectively bypasses the BRG. A software Write to either
0001h
the Low- or High-byte registers for the BRG Divisor Latch causes both the Low and High
bytes to load into the BRG counter, and causes the count to restart.
The divisor registers can only be accessed if bit 7 of the UART Line Control register
(UARTx_LCTL) is set to 1. After reset, this bit is reset to 0.
PS015313-0508
Universal Asynchronous Receiver/Transmitter
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