EZ80F92AZ020EC00TR Zilog, EZ80F92AZ020EC00TR Datasheet - Page 175
EZ80F92AZ020EC00TR
Manufacturer Part Number
EZ80F92AZ020EC00TR
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F92AZ020EC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
EZ80F92AZ020EC00T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS015313-0508
ZDA
ZCL
ZDA
ZCL
Operation of the eZ80F92 Device During ZDI Breakpoints
ZDI Address
ZDI Address
lsb of
ZDI Block Read
A Block Read operation is initiated the same as a single-byte Read; however, the ZDI
master continues to clock in the next byte from the ZDI slave as the ZDI slave continues to
output data. The ZDI register address counter increments with each Read. If the ZDI regis-
ter address reaches the end of the Read Only ZDI register address space (
stops incrementing.
lsb of
If the ZDI forces the CPU to BREAK, only the CPU suspends operation. The system clock
continues to operate and drive other peripherals. Those peripherals that can operate auton-
omously from the CPU may continue to operate, if so enabled. For example, the Watchdog
Timer and Programmable Reload Timers continue to count during a ZDI BREAK point.
When using the ZDI interface, any Write or Read operations of peripheral registers in the
I/O address space produces the same effect as Read or Write operations using the CPU.
A0
7
A0
7
Read
Read
8
8
Byte Separator
Byte Separator
Single-Bit
Single-Bit
Figure 44.ZDI Single-Byte Data Read Timing
0/1
9
0/1
9
Figure 45.ZDI Block Data Read Timing
of DATA
of DATA
Figure 45
msb
Byte 1
D7
msb
1
D7
1
D6
2
D6
2
displays the ZDI’s Block Read timing.
D5
3
D5
3
ZDI Data Byte
D4
ZDI Data Bytes
4
D1
7
of DATA
Byte 1
D3
5
D0
lsb
8
Byte Separator
Single-Bit
D2
0/1
6
9
of DATA
Byte 2
D1
msb
7
D7
1
Product Specification
of DATA
eZ80F92/eZ80F93
D0
lsb
8
D6
Zilog Debug Interface
2
START Signal
20h
End of Data
or New ZDI
1
), the address
9
1
9
168
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