EZ80F92AZ020EC00TR Zilog, EZ80F92AZ020EC00TR Datasheet - Page 16
EZ80F92AZ020EC00TR
Manufacturer Part Number
EZ80F92AZ020EC00TR
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F92AZ020EC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
EZ80F92AZ020EC00T
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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued)
PS015313-0508
Pin No Symbol
25
26
27
28
29
30
31
32
ADDR20
ADDR21
ADDR22
ADDR23
CS0
CS1
CS2
CS3
Function
Address Bus
Address Bus
Address Bus
Address Bus
Chip Select 0
Chip Select 1
Chip Select 2
Chip Select 3
Signal Direction
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output, Active Low
Output, Active Low
Output, Active Low
Output, Active Low
Description
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
CS0 Low indicates that an access is
occurring in the defined CS0 memory or
I/O address space.
CS1 Low indicates that an access is
occurring in the defined CS1 memory or
I/O address space.
CS2 Low indicates that an access is
occurring in the defined CS2 memory or
I/O address space.
CS3 Low indicates that an access is
occurring in the defined CS3 memory or
I/O address space.
Product Specification
Architectural Overview
9
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