EZ80F92AZ020EC00TR Zilog, EZ80F92AZ020EC00TR Datasheet - Page 62
EZ80F92AZ020EC00TR
Manufacturer Part Number
EZ80F92AZ020EC00TR
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F92AZ020EC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
EZ80F92AZ020EC00T
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eZ80F92/eZ80F93
Product Specification
55
T1
T2
T
T3
CLK
System Clock
ADDR[23:0]
DATA[7:0]
CSx
RD
WAIT
WR
MREQ
or IORQ
®
Figure 10. Example: Z80
Bus Mode Write Timing
Intel
Bus Mode
TM
Chip selects configured for Intel bus mode modify the CPU bus signals to duplicate a four-
state memory transfer similar to that found on Intel-style microcontrollers. The bus signals
and eZ80F92 device pins are mapped as displayed in
Figure 11
on page 56. In Intel bus
mode, you can select either multiplexed or nonmultiplexed address and data buses. In non-
multiplexed operation, the address and data buses are separate. In multiplexed operation,
the lower byte of the address, ADDR[7:0], also appears on the data bus, DATA[7:0], dur-
ing State T1 of the Intel bus mode cycle. During multiplexed operation, the lower byte of
the address bus also appears on the address bus in addition to the data bus.
PS015313-0508
Chip Selects and Wait States
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