EZ80F92AZ020EC00TR Zilog, EZ80F92AZ020EC00TR Datasheet - Page 156
EZ80F92AZ020EC00TR
Manufacturer Part Number
EZ80F92AZ020EC00TR
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F92AZ020EC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
EZ80F92AZ020EC00T
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PS015313-0508
Table 80. I
When all bytes are transmitted, the microcontroller should write a 1 to the STP bit in the
I2C_CTL register. The I
to the idle state.
Master Receive
In MASTER RECEIVE mode, the I
ter.
After the START condition is transmitted, the IFLG bit is 1 and the status code
loaded in the I2C_SR register. The I2C_DR register should be loaded with the slave
address (or the first part of a 10-bit slave address), with the lsb set to 1 to signify a Read.
The IFLG bit should be cleared to 0 as a prompt for the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit are
transmitted, the IFLG bit is set and one of the status codes listed in
I2C_SR register.
Table 81. I
Code I
30h
38h
Code
40h
R = Read bit; that is, the lsb is set to 1.
Data byte transmitted,
ACK not received
Arbitration lost
2
C State
2
2
I
Addr + R
transmitted, ACK
received
C Master Transmit Status Codes For Data Bytes (Continued)
C Master Receive Status Codes
2
C State
2
C then transmits a STOP condition, clears the STP bit and returns
Microcontroller Response Next I
Same as code 28h
Clear IFLG
Or set STA, clear IFLG
Microcontroller Response Next I
For a 7-bit address,
clear IFLG, AAK = 0
Or clear IFLG, AAK = 1
For a 10-bit address
Write extended address
byte to DATA, clear IFLG
2
C receives a number of bytes from a slave transmit-
Same as code 28h
Return to idle
Transmit START when bus
free
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit extended
address byte
Product Specification
2
Table 81
C Action
I2C Serial I/O Interface
2
C Action
is in the
08h
is
149
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