EZ80F92AZ020EC00TR Zilog, EZ80F92AZ020EC00TR Datasheet - Page 186
EZ80F92AZ020EC00TR
Manufacturer Part Number
EZ80F92AZ020EC00TR
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F92AZ020EC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
EZ80F92AZ020EC00T
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PS015313-0508
ZDI Bus Control Register
The ZDI Bus Control register controls bus requests during DEBUG mode. It enables or
disables bus acknowledge in ZDI DEBUG mode and allows ZDI to force assertion of the
BUSACK signal. This register should only be written during ZDI DEBUG mode (that is,
following a BREAK). See
Table 100. ZDI Bus Control Register(ZDI_BUS_CTL = 17h in the ZDI Register Write
Only Address Space)
Bit
Reset
CPU Access
Note: W = Write Only.
Bit Position
7
ZDI_BUSAK_EN
6
ZDI_BUSAK
[5:0]
Value
0
1
0
1
000000
Table
W
7
0
100.
Description
Bus requests by external peripherals using the BUSREQ
pin are ignored. The bus acknowledge signal, BUSACK,
is not asserted in response to any bus requests.
Bus requests by external peripherals using the BUSREQ
pin are accepted. A bus acknowledge occurs at the end
of the current ZDI operation. The bus acknowledge is
indicated by asserting the BUSACK pin in response to a
bus request.
Deassert the bus acknowledge pin (BUSACK) to return
control of the address and data buses back to ZDI.
Assert the bus acknowledge pin (BUSACK) to pass
control of the address and data buses to an external
peripheral.
Reserved.
W
6
0
W
5
0
W
4
0
W
3
0
Product Specification
W
2
0
eZ80F92/eZ80F93
Zilog Debug Interface
W
1
0
W
0
0
179
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