ST72F521AR9TC STMicroelectronics, ST72F521AR9TC Datasheet - Page 134

• Manufacturer Part Number: ST72F521AR9TC
• Description: IC MCU 8BIT 60K FLASH 64-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F521AR9TC

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: 497-6453 - BOARD EVAL BASED ON ST7LNBX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
– ERROR. The error management as described in
Figure 71. CAN Error State Diagram
134/215
the CAN protocol is completely handled by hard-
ware using 2 error counters which get increment-
ed or decremented according to the error
condition. Both of them may be read by the appli-
When 128 * 11 recessive bits occur:
- the BOFF bit gets cleared
- the TECR register gets cleared
- the RECR register gets cleared
ERROR ACTIVE
When TECR or RECR > 127, the EPSV bit gets set
the EPSV bit gets cleared
When TECR and RECR < 128,
BUS OFF
cation to determine the stability of the network.
Moreover, as one of the node status bits (EPSV
or BOFF of the CSR register) changes, an inter-
rupt is generated if the SCIE bit is set in the ICR
Register. Refer to
ERROR PASSIVE
When TECR > 255 the BOFF bit gets set
and the EPSV bit gets cleared
Figure
71.