ST72F521AR9TC STMicroelectronics, ST72F521AR9TC Datasheet - Page 140

• Manufacturer Part Number: ST72F521AR9TC
• Description: IC MCU 8BIT 60K FLASH 64-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F521AR9TC

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: 497-6453 - BOARD EVAL BASED ON ST7LNBX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
10.8.4.2 Paged Registers
LAST IDENTIFIER HIGH REGISTER (LIDHR)
Read/Write
Reset Value: Undefined
LID[10:3] are the most significant 8 bits of the last
Identifier read on the CAN bus.
LAST IDENTIFIER LOW REGISTER (LIDLR)
Read/Write
Reset Value: Undefined
LID[2:0] are the least significant 3 bits of the last
Identifier read on the CAN bus.
LRTR is the last Remote Transmission Request bit
read on the CAN bus.
LDLC[3:0] is the last Data Length Code read on the
CAN bus.
140/215
LID10
LID2
7
7
LID9
LID1
LID8
LID0
LRTR
LID7
LDLC
LID6
3
LDLC
LID5
2
LDLC
LID4
1
LDLC
LID3
0
0
0
TRANSMIT ERROR COUNTER REG. (TECR)
Read Only
Reset Value: 00h
TEC[7:0] is the least significant byte of the 9-bit
Transmit Error Counter implementing part of the
fault confinement mechanism of the CAN protocol.
In case of an error during transmission, this counter
is incremented by 8. It is decremented by 1 after
every successful transmission. When the counter
value exceeds 127, the CAN controller enters the
error passive state. When a value of 256 is reached,
the CAN controller is disconnected from the bus.
RECEIVE ERROR COUNTER REG. (RECR)
Page: 00h — Read Only
Reset Value: 00h
REC[7:0] is the Receive Error Counter implement-
ing part of the fault confinement mechanism of the
CAN protocol. In case of an error during reception,
this counter is incremented by 1 or by 8 depending
on the error condition as defined by the CAN stand-
ard. After every successful reception the counter is
decremented by 1 or reset to 120 if its value was
higher than 128. When the counter value exceeds
127, the CAN controller enters the error passive
state.
IDENTIFIER HIGH REGISTERS (IDHRx)
Read/Write
Reset Value: Undefined
ID[10:3] are the most significant 8 bits of the 11-bit
message identifier.The identifier acts as the mes-
sage’s name, used for bus access arbitration and
acceptance filtering.
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
TEC7
ID10
7
7
7
TEC6
ID9
TEC5
ID8
TEC4
ID7
TEC3
ID6
TEC2
ID5
TEC1
ID4
TEC0
ID3
0
0
0