ST72F521AR9TC STMicroelectronics, ST72F521AR9TC Datasheet - Page 141

• Manufacturer Part Number: ST72F521AR9TC
• Description: IC MCU 8BIT 60K FLASH 64-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F521AR9TC

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: 497-6453 - BOARD EVAL BASED ON ST7LNBX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CONTROLLER AREA NETWORK (Cont’d)
IDENTIFIER LOW REGISTERS (IDLRx)
Read/Write
Reset Value: Undefined
ID[2:0] are the least significant 3 bits of the 11-bit
message identifier.
RTR is the Remote Transmission Request bit. It is
set to indicate a remote frame and reset to indicate
a data frame.
DLC[3:0] is the Data Length Code. It gives the
number of bytes in the data field of the mes-
sage.The valid range is 0 to 8.
DATA REGISTERS (DATA0-7x)
Read/Write
Reset Value: Undefined
DATA[7:0] is a message data byte. Up to eight such
bytes may be part of a message. Writing to byte
DATA7 initiates a transmit request and should al-
ways be done even when DATA7 is not part of the
message.
DATA
ID2
7
7
7
DATA
ID1
6
DATA
ID0
5
DATA
RTR
4
DATA
DLC3
3
DATA
DLC2
2
DLC1
DATA
1
DLC0
DATA
0
0
0
BUFFER CONTROL/STATUS REGs. (BCSRx)
Read/Write
Reset Value: 00h
Bit 3 = ACC Acceptance Code
−
Set by hardware with the id of the highest priority
filter which accepted the message stored in the
buffer.
ACC = 0: Match for Filter/Mask0. Possible match
for Filter/Mask1.
ACC = 1: No match for Filter/Mask0 and match for
Filter/Mask1.
Reset by hardware when either RDY or RXIF gets
reset.
Bit 2 = RDY Message Ready
−
Set by hardware to signal that a new error-free
message is available (LOCK = 0) or that a trans-
mission request is pending (LOCK = 1).
Cleared by software when LOCK = 0 to release
the buffer and to clear the corresponding RXIF bit
in the Interrupt Status Register.
Cleared by hardware when LOCK = 1 to indicate
that the transmission request has been serviced or
cancelled.
Bit 1 = BUSY Busy Buffer
−
Set by hardware when the buffer is being filled
(LOCK = 0) or emptied (LOCK = 1) and reset after
the 2nd intermission bit.
Reset by hardware when the buffer is not ac-
cessed by the CAN core for transmission nor re-
ception purposes.
Bit 0 = LOCK Lock Buffer
−
Set by software to lock a buffer. No more message
can be received into the buffer thus preserving its
content and making it available for transmission.
Cleared by software to make the buffer available
for reception. Cancels any pending transmission
request.
Cleared by hardware once a message has been
successfully transmitted provided the early trans-
mit interrupt mode is on. Left untouched otherwise.
Note that in order to prevent any message corrup-
tion or loss of context, LOCK cannot be set nor re-
set while BUSY is set. Trying to do so will result in
LOCK not changing state.
Read Only
Read/Clear
Read Only
Read/Set/Clear
7
0
0
0
0
ST72F521, ST72521B
ACC
RDY
BUSY LOCK
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