ST72F521AR9TC STMicroelectronics, ST72F521AR9TC Datasheet - Page 35
![IC MCU 8BIT 60K FLASH 64-TQFP](/photos/6/76/67655/497-64-tqfp_sml.jpg)
ST72F521AR9TC
Manufacturer Part Number
ST72F521AR9TC
Description
IC MCU 8BIT 60K FLASH 64-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F521M9T6.pdf
(215 pages)
Specifications of ST72F521AR9TC
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TQFP, 64-VQFP
For Use With
497-6453 - BOARD EVAL BASED ON ST7LNBX
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 20. Concurrent Interrupt Management
Figure 21. Nested Interrupt Management
11 / 10
11 / 10
MAIN
MAIN
Figure
RIM
RIM
19.
IT2
IT2
IT1
IT1
IT4
TRAP
TRAP
IT1
IT4
IT0
IT0
7.4 CONCURRENT & NESTED MANAGEMENT
The following
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
IT3
IT3
IT1
21. The interrupt hardware priority is given
IT4
IT2
Figure 20
10
10
SOFTWARE
PRIORITY
LEVEL
SOFTWARE
PRIORITY
LEVEL
MAIN
MAIN
ST72F521, ST72521B
and
3
3
3
3
3
3
3/0
3
3
2
1
3
3
3/0
Figure 21
I1
I1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 0
0 1
1 1
1 1
show two
I0
I0
35/215
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