W77E058A40DL Nuvoton Technology Corporation of America, W77E058A40DL Datasheet - Page 67
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W77E058A40DL
Manufacturer Part Number
W77E058A40DL
Description
IC MCU 8-BIT 32K FLASH 40-DIP
Manufacturer
Nuvoton Technology Corporation of America
Series
W77r
Specifications of W77E058A40DL
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, Serial Port
Peripherals
POR, WDT
Number Of I /o
32
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP
Cpu Family
W77
Device Core
8051
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
UART
Total Internal Ram Size
1KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
40
Package Type
PDIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
W77E058A40DL
Manufacturer:
WINBOND
Quantity:
4 500
Company:
Part Number:
W77E058A40DL
Manufacturer:
WINBOND
Quantity:
5
Part Number:
W77E058A40DL
Manufacturer:
WINBOND/华邦
Quantity:
20 000
When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine
cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the
first write (AAh), then the timed access window is opened. It remains open for 3 machine cycles,
during which the user may write to the protected bits. Once the window closes the procedure must be
repeated to access the other protected bits.
Examples of Timed Assessing are shown below
Example 1: Valid access
Example 2: Valid access
Example 3: Valid access
Example 4: Invalid access
Example 5: Invalid Access
In the first two examples, the writing to the protected bits is done before the 3 machine cycle window
closes. In Example 3, however, the writing to the protected bit occurs after the window has closed,
and so there is effectively no change in the status of the protected bit. In Example 4, the second write
to TA occurs 4 machine cycles after the first write, therefore the timed access window in not opened at
all, and the write to the protected bit fails.
MOV
MOV
MOV
MOV
MOV
NOP
SETB EWT
MOV
MOV
ORL
MOV
MOV
NOP
NOP
CLR
MOV
NOP
MOV
SETB EWT
TA, #0AAh
TA, #055h
WDCON, #00h 3 M/C
TA, #0AAh
TA, #055h
TA, #0Aah
TA, #055h
WDCON, #00000010B 3M/C
TA, #0AAh
TA, #055h
POR
TA, #0AAh
TA, #055h
3 M/C
3 M/C
3 M/C
1 M/C
2 M/C
3 M/C
3 M/C
3 M/C
3 M/C
1 M/C
1 M/C
2 M/C
3 M/C
1 M/C
3 M/C
2 M/C
3 M/C
- 67 -
Note: M/C = Machine Cycles
Publication Release Date: February 17, 2005
W77E58
Revision A6