ST10F269Z2Q6 STMicroelectronics, ST10F269Z2Q6 Datasheet - Page 37

• Manufacturer Part Number: ST10F269Z2Q6
• Description: MCU 16BIT 256K FLASH 144PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269Z2Q6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Controller Family/series: ST10
• No. Of I/o's: 111
• Ram Memory Size: 12KB
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Embedded Interface Type: CAN, SSC, USART
• Rohs Compliant: Yes
• Processor Series: ST10F26x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 0.3 V to 4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4833

ST10F269
6.1.1 - Features
6.1.1.1 - Enhanced Addressing Capabilities
– New addressing modes including a double indi-
– Parallel Data Move: this mechanism allows one
– New transfer instructions CoSTORE (for fast ac-
6.1.1.2 - Multiply-Accumulate Unit
– One-cycle execution for all MAC operations.
Figure 10 : MAC Unit Architecture
Note: * Shared with standard ALU.
rect addressing mode with pointer post-modifi-
cation.
operand move during Multiply-Accumulate in-
structions without penalty.
cess to the MAC SFRs) and CoMOV (for fast
memory to memory table transfer).
Controller
ST10 CPU
Interrupt
GPR Pointers *
IDX0 Pointer
IDX1 Pointer
QR0 GPR Offset Register
QR1 GPR Offset Register
QX0 IDX Offset Register
QX1 IDX Offset Register
Repeat Unit
MRW
Control Unit
MCW
Concatenation
– 16 x 16-bit signed/unsigned parallel multiplier.
– 40-bit signed arithmetic unit with automatic sat-
– 40-bit accumulator.
– 8-bit left/right shifter.
– Full instruction set with multiply and multiply-ac-
6.1.1.3 - Program Control
– Repeat Unit: allows some MAC co-processor in-
– MAC interrupt (Class B Trap) on MAC condition
6 - CENTRAL PROCESSING UNIT (CPU)
MSW
uration mode.
cumulate, 32-bit signed arithmetic and compare
instructions.
structions to be repeated up to 8192 times. Re-
peated instructions may be interrupted.
flags.
Flags MAE
32
40
0h
Sign Extend
Operand 1
Scaler
40
40
Mux
Mux
40-bit Signed Arithmetic Unit
A
signed/unsigned
16
40
08000h
Multiplier
16 x 16
32
MAH
8-bit Left/Right
16
40
40
Shifter
Operand 2
40
0h
MAL
40
Mux
B
40
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