C8051F333-GMR Silicon Laboratories Inc, C8051F333-GMR Datasheet - Page 141
![IC 8051 MCU 4K FLASH 20MLP](/photos/16/2/160285/qfn-20_sml.jpg)
C8051F333-GMR
Manufacturer Part Number
C8051F333-GMR
Description
IC 8051 MCU 4K FLASH 20MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F333-GMR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F330DK
Minimum Operating Temperature
- 40 C
For Use With
336-1451 - ADAPTER PROGRAM TOOLSTICK F330
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F333-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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ARBLOST
TXMODE
MASTER
ACKRQ
STO
ACK
STA
Bit
SI
• A START is generated.
• START is generated.
• SMB0DAT is written before the start of an
• A START followed by an address byte is
• A STOP is detected while addressed as a
• Arbitration is lost due to a detected STOP.
• A byte has been received and an ACK
• A repeated START is detected as a MASTER
• SCL is sensed low while attempting to gener-
• SDA is sensed low while transmitting a ‘1’
• The incoming ACK value is low
• A START has been generated.
• Lost arbitration.
• A byte has been transmitted and an
• A byte has been received.
• A START or repeated START followed by a
• A STOP has been received.
Table 15.3. Sources for Hardware Changes to SMB0CN
SMBus frame.
received.
slave.
response value is needed.
when STA is low (unwanted repeated START).
ate a STOP or repeated START condition.
(excluding ACK bits).
(ACKNOWLEDGE).
ACK/NACK received.
slave address + R/W has been received.
Set by Hardware When:
Rev. 1.7
C8051F330/1/2/3/4/5
• A STOP is generated.
• Arbitration is lost.
• A START is detected.
• Arbitration is lost.
• SMB0DAT is not written before the
• Must be cleared by software.
• A pending STOP is generated.
• After each ACK cycle.
• Each time SI is cleared.
• The incoming ACK value is high (NOT
• Must be cleared by software.
start of an SMBus frame.
ACKNOWLEDGE).
Cleared by Hardware When:
145
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