C8051F333-GMR Silicon Laboratories Inc, C8051F333-GMR Datasheet - Page 68
![IC 8051 MCU 4K FLASH 20MLP](/photos/16/2/160285/qfn-20_sml.jpg)
C8051F333-GMR
Manufacturer Part Number
C8051F333-GMR
Description
IC 8051 MCU 4K FLASH 20MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F333-GMR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F330DK
Minimum Operating Temperature
- 40 C
For Use With
336-1451 - ADAPTER PROGRAM TOOLSTICK F330
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F333-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
9.
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
four 16-bit counter/timers (see description in
in
Special Function Register (SFR) address space
tion
directly with the analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram).
The CIP-51 includes the following features:
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
Section
- Fully Compatible with MCS-51 Instruction
- 25 MIPS Peak Throughput with 25 MHz
- 0 to 25 MHz Clock Frequency
14). The CIP-51 also includes on-chip debug hardware (see description in
CIP-51 Microcontroller
Set
Clock
16), an Enhanced SPI (see description in
RESET
CLOCK
STOP
IDLE
Figure 9.1. CIP-51 Block Diagram
ACCUMULATOR
PROGRAM COUNTER (PC)
CONTROL
PSW
PRGM. ADDRESS REG.
LOGIC
POWER CONTROL
PC INCREMENTER
DATA POINTER
REGISTER
BUFFER
TMP1
PIPELINE
Section
ALU
(Section
Rev. 1.7
TMP2
DATA BUS
DATA BUS
D8
D8
D8
18), an enhanced full-duplex UART (see description
Section
A16
D8
D8
D8
D8
B REGISTER
9.2.6), and 17 Port I/O (see description in
REGISTER
INTERFACE
INTERFACE
INTERRUPT
INTERFACE
- 256 Bytes of Internal RAM
- 17 Port I/O
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
ADDRESS
MEMORY
SRAM
BUS
SFR
C8051F330/1/2/3/4/5
17), 256 bytes of internal RAM, 128 byte
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
SRAM
MEM_CONTROL
EMULATION_IRQ
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
SYSTEM_IRQs
Section
20), and interfaces
Sec-
71