S9S12P96J0MFT Freescale Semiconductor, S9S12P96J0MFT Datasheet - Page 389

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S9S12P96J0MFT

Manufacturer Part Number
S9S12P96J0MFT
Description
MCU 96K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of S9S12P96J0MFT

Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
In
perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data
recovery is successful.
In
at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived
bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
Freescale Semiconductor
Figure
Figure
RT Clock Count
Reset RT Clock
RT Clock Count
Reset RT Clock
RT Clock
RT Clock
Samples
Samples
11-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample
11-23, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the
RXD
RXD
1
1
1
1
1
1
1
0
1
Figure 11-22. Start Bit Search Example 1
Figure 11-23. Start Bit Search Example 2
0
1
S12P-Family Reference Manual, Rev. 1.13
1
1
1
0
0
Perceived Start Bit
0
0
0
0
0
0
Actual Start Bit
Start Bit
0
0
0
Serial Communication Interface (S12SCIV5)
0
LSB
LSB
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