S9S12P96J0MFT Freescale Semiconductor, S9S12P96J0MFT Datasheet - Page 73

• Manufacturer Part Number: S9S12P96J0MFT
• Description: MCU 96K FLASH AUTO 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12P96J0MFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
2.3.18
Freescale Semiconductor
Address 0x0242
7-6, 3-1
Write: Anytime
DDRT
DDRT
DDRT
Field
Field
PTIT
Reset
7-0
4,0
5
W
R
Port T input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. In this case
the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. Else the API_EXTCLK forces the I/O state
to be an output if enabled. In these cases the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. In these cases the data direction bit will not
change.
1 Associated pin is configured as output
0 Associated pin is configured as input
DDRT7
Port T Data Direction Register (DDRT)
0
7
DDRT6
0
6
Figure 2-16. Port T Data Direction Register (DDRT)
Table 2-16. DDRT Register Field Descriptions
Table 2-15. PTIT Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
DDRT5
5
0
DDRT4
0
4
Description
Description
DDRT3
0
3
DDRT2
0
2
Port Integration Module (S12PPIMV1)
Access: User read/write
DDRT1
0
1
DDRT0
0
0
73
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