S9S12P96J0MFT Freescale Semiconductor, S9S12P96J0MFT Datasheet - Page 95

• Manufacturer Part Number: S9S12P96J0MFT
• Description: MCU 96K FLASH AUTO 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12P96J0MFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
1. Read: Anytime
2.3.54
2.3.55
Freescale Semiconductor
Address 0x026D
Address 0x026E
7-6, 2-0
7-6, 2-0
Write: Anytime
Write: Anytime
Read: Anytime.
PPSJ
Field
Field
PIEJ
Reset
Reset
W
W
R
R
Port J pull device select—Configure pull device and pin interrupt edge polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 A pull-down device is selected; rising edge selected
0 A pull-up device is selected; falling edge selected
Port J interrupt enable—
This bit enables or disables on the edge sensitive pin interrupt on the associated pin.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
PPSJ7
PIEJ7
Port J Polarity Select Register (PPSJ)
Port J Interrupt Enable Register (PIEJ)
0
0
7
7
PPSJ6
PIEJ6
0
0
6
6
Figure 2-53. Port J Interrupt Enable Register (PIEJ)
Figure 2-52. Port J Polarity Select Register (PPSJ)
Table 2-48. PPSJ Register Field Descriptions
Table 2-49. PIEJ Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
5
0
0
5
0
0
0
0
0
0
4
4
Description
Description
0
0
0
0
3
3
PPSJ2
PIEJ2
0
0
2
2
Port Integration Module (S12PPIMV1)
Access: User read/write
Access: User read/write
PPSJ1
PIEJ1
0
0
1
1
PPSJ0
PIEJ0
0
0
0
0
95
(1)
(1)