TMP86FH46ANG(Z) Toshiba, TMP86FH46ANG(Z) Datasheet - Page 37
TMP86FH46ANG(Z)
Manufacturer Part Number
TMP86FH46ANG(Z)
Description
IC MCU 8BIT FLASH 16KB 42-SDIP
Manufacturer
Toshiba
Series
TLCS-870/Cr
Datasheet
1.TMP86FH46ANGZ.pdf
(214 pages)
Specifications of TMP86FH46ANG(Z)
Core Processor
870/C
Core Size
8-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
LED, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-SDIP (0.600", 15.24mm)
Processor Series
TLCS-870
Core
870/C
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SIO, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
33
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
BMSKTOPAS86FH47(AND), BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP86C909XB - EMULATION CHIP FOR TMP86F SDIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
TMP86FH46ANGZ
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2.2.4.3
timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes.
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base
Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals.
1. Timing generator stops feeding clock to peripherals except TBT.
2. The data memory, CPU registers, program status word and port output latches are all held in the
3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and
status in effect before IDLE0 and SLEEP0 modes were entered.
SLEEP0 modes.
(Normal release mode)
Figure 2-12 IDLE0 and SLEEP0 Modes
No
No
No
No
CPU and WDT are halted
Execution of the instruction
which follows the IDLE0,
Page 23
Starting IDLE0, SLEEP0
Stopping peripherals
Interrupt processing
SLEEP0 modes start
modes by instruction
TBTCR<TBTEN>
by instruction
TBT interrupt
source clock
Reset input
IMF = "1"
instruction
enable
falling
= "1"
edge
TBT
Yes
Yes
No
Yes
Yes (Interrupt release mode)
Yes
Reset
TMP86FH46ANG
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