HD64F3672FPV Renesas Electronics America, HD64F3672FPV Datasheet
HD64F3672FPV
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HD64F3672FPV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8/300H Series 16 Software Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Rev. 3.00 Dec 13, 2004 page iv of xiv ...
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The H8/300H Series is built around a 32-bit H8/300H CPU core with sixteen 16-bit registers, a concise, optimized instruction set designed for high-speed operation, and a 16-Mbyte linear address space. For easy migration from the H8/300 Series, the instruction set ...
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Rev. 3.00 Dec 13, 2004 page vi of xiv ...
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Main Revisions for this Edition Item Page All Revisions (See Manual for Details) All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names changed to Renesas Technology Corp. Designation for categories changed from “series” to “group” Rev. ...
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Rev. 3.00 Dec 13, 2004 page viii of xiv ...
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Section 1 CPU .................................................................................................................... 1.1 Overview ........................................................................................................................... 1.1.1 Features ................................................................................................................ 1.1.2 Differences from H8/300 CPU............................................................................. 1.2 CPU Operating Modes ...................................................................................................... 1.3 Address Space ................................................................................................................... 1.4 Register Configuration ...................................................................................................... 1.4.1 Overview .............................................................................................................. 1.4.2 General Registers ................................................................................................. 1.4.3 Control Registers.................................................................................................. 10 1.4.4 ...
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AND (L) .......................................................................................................... 49 2.2.5 ANDC.............................................................................................................. 50 2.2.6 BAND.............................................................................................................. 51 2.2.7 Bcc................................................................................................................... 52 2.2.8 BCLR............................................................................................................... 54 2.2.9 BIAND ............................................................................................................ 56 2.2.10 BILD................................................................................................................ 57 2.2.11 BIOR ............................................................................................................... 58 2.2.12 BIST ................................................................................................................ 59 2.2.13 BIXOR............................................................................................................. 60 2.2.14 BLD ................................................................................................................. 61 ...
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JMP.................................................................................................................. 107 2.2.33 JSR................................................................................................................... 108 2.2.34 (1) LDC (B)........................................................................................................... 110 2.2.34 (2) LDC (W).......................................................................................................... 111 2.2.35 (1) MOV (B) ......................................................................................................... 113 2.2.35 (2) MOV (W) ........................................................................................................ 114 2.2.35 (3) MOV (L).......................................................................................................... 115 2.2.35 (4) MOV (B) ......................................................................................................... 116 2.2.35 ...
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ROTXL (B) ..................................................................................................... 155 2.2.49 (2) ROTXL (W) .................................................................................................... 156 2.2.49 (3) ROTXL (L)...................................................................................................... 157 2.2.50 (1) ROTXR (B) ..................................................................................................... 158 2.2.50 (2) ROTXR (W) .................................................................................................... 159 2.2.50 (3) ROTXR (L) ..................................................................................................... 160 2.2.51 RTE ................................................................................................................. 161 2.2.52 ...
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Section 3 Processing States 3.1 Overview ........................................................................................................................... 245 3.2 Program Execution State ................................................................................................... 246 3.3 Exception-Handling State.................................................................................................. 246 3.3.1 Types of Exception Handling and Their Priority ................................................. 247 3.3.2 Exception-Handling Sequences............................................................................ 248 3.4 Bus-Released State ............................................................................................................ 250 3.5 Reset State ...
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Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 1 CPU 16 ÷ 8-bit register-register divide: 875 ns 16 16-bit register-register multiply: 1375 ns 32 ÷ 16-bit register-register divide: 1375 ns Two CPU operating modes Normal mode Advanced mode Low-power mode Transition to power-down state by SLEEP instruction ...
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CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports Mbytes. The mode is selected at the mode pins of the microcontroller. ...
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Section 1 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 Figure 1.2 Exception Vector Table (normal mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address to specify ...
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Advanced Mode In advanced mode the exception vector table and stack structure differ from the H8/300 CPU. Address Space Mbytes can be accessed linearly. Extended Registers (En): The extended registers (E0 to E7) can be used ...
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Section 1 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword ...
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Address Space Figure 1.6 shows a memory map of the H8/300H CPU. (a) Normal mode H'0000 H'FFFF (b) Advanced mode H'000000 H'FFFFFF Figure 1.6 Memory Map Rev. 3.00 Dec 13, 2004 page 7 of 258 Section 1 CPU REJ09B0213-0300 ...
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Section 1 CPU 1.4 Register Configuration 1.4.1 Overview The H8/300H CPU has the internal registers shown in figure 1.7. There are two types of registers: general and extended registers, and control registers. General registers (Rn) and extended registers (En) 15 ...
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General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, ...
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Section 1 CPU SP (ER7) 1.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will ...
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Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, ...
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Section 1 CPU 1.5 Data Formats The H8/300H CPU can process 1-bit, 4-bit, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte ...
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Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: ...
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Section 1 CPU 1.5.2 Memory Data Formats Figure 1.11 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address ...
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Instruction Set 1.6.1 Overview The H8/300H CPU has 62 types of instructions, which are classified by function in table 1.1. For a detailed description of each instruction see section 2.2, Instruction Descriptions. Table 1.1 Instruction Classification Function Instructions MOV, ...
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Section 1 CPU 1.6.2 Instructions and Addressing Modes Table 1.2 indicates the instructions available in the H8/300H CPU. Table 1.2 Instruction Set Overview Function Instruction Data MOV BWL BWL BWL BWL BWL BWL transfer POP, PUSH — MOVFPE, — MOVTPE ...
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Function Instruction Branch Bcc, BSR — JMP, JSR — RTS — System TRAPA — control RTE — SLEEP — LDC B STC — ANDC, B ORC, XORC NOP — Block data EEPMOV.B — transfer EEPMOV.W — Legend: B: Byte W: ...
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Section 1 CPU 1.6.3 Tables of Instructions Classified by Function Table 1.3 summarizes the instructions in each functional category. The notation used in table 1.3 is defined next. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General ...
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Table 1.3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH Arithmetic ADD operations SUB ADDX SUBX INC DEC Size * Function B/W/L (EAs) Rd, Rs (EAd) Moves data between two general registers or between a ...
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Section 1 CPU Type Instruction Arithmetic ADDS operations SUBS DAA DAS MULXS MULXU DIVXS DIVXU CMP NEG Rev. 3.00 Dec 13, 2004 page 20 of 258 REJ09B0213-0300 Size * Function L Rd ± 1 Rd, Rd ± 2 Adds or ...
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Type Instruction Arithmetic EXTS operations EXTU Logic operations AND OR XOR NOT Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Size * Function W/L Rd (sign extension) Extends byte data in the lower 8 bits of a 16-bit ...
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Section 1 CPU Type Instruction Bit-manipulation BSET instructions BCLR BNOT BTST BAND BIAND Rev. 3.00 Dec 13, 2004 page 22 of 258 REJ09B0213-0300 Size * Function B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or ...
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Type Instruction Bit-manipulation BOR instructions BIOR BXOR BIXOR BLD BILD BST BIST Size * Function B C (<bit-No.> of <EAd>) ORs the carry flag with a specified bit in a general register or memory operand and stores the result in ...
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Section 1 CPU Type Instruction Branching Bcc instructions JMP BSR JSR RTS Rev. 3.00 Dec 13, 2004 page 24 of 258 REJ09B0213-0300 Size * Function — Branches to a specified address if a specified condition is true. The branching conditions ...
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Type Instruction System control TRAPA instructions RTE SLEEP LDC STC ANDC ORC XORC NOP Size * Function — Starts trap-instruction exception handling. — Returns from an exception-handling routine. — Causes a transition to the power-down state. B/W (EAs) CCR Moves ...
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Section 1 CPU Type Instruction Block data EEPMOV.B transfer instruction EEPMOV.W Note: * Size refers to the operand size. B: Byte W: Word L: Longword 1.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists ...
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Condition Field: Specifies the branching condition of Bcc instructions. Figure 1.12 shows examples of instruction formats. (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension op (4) Operation field, ...
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Section 1 CPU 1.6.5 Addressing Modes and Effective Address Calculation (1) Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 1.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use ...
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Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of a memory operand. After the ...
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Section 1 CPU 7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit program counter (PC) contents ...
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Section 2 Instruction Descriptions 2.1 Tables and Symbols This section explains how to read the tables describing each instruction. Note that the descriptions of some instructions extend over two pages or more. Mnemonic (full name): Gives the full and mnemonic ...
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Section 2 Instruction Descriptions 2.1.1 Assembler Format Example: ADD. B <EAs>, Rd Size Mnemonic The operand size is byte (B), word (W), or longword (L). Some instructions are restricted to a limited set of operand sizes. The symbol <EA> indicates ...
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Operation The symbols used in the operation descriptions are defined as follows. Symbol Meaning General destination register * Rd General source register * Rs General register * Rn ERd General destination register (address register or 32-bit register) ERs General ...
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Section 2 Instruction Descriptions 2.1.3 Condition Code The symbols used in the condition-code description are defined as follows. Symbol Meaning Changes according to the result of the instruction Undetermined (no guaranteed value Always cleared to 0 — Not ...
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Register Specification Address Register Specification: When a general register is used as an address register [@ERn, @(d:16, ERn), @(d:24, ERn), @ERn+, or @–ERn], the register is specified by a 3-bit register field (ers or erd). The lower 24 bits ...
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Section 2 Instruction Descriptions 2.1.6 Bit Data Access in Bit Manipulation Instructions Bit data is accessed as the n-th bit ( … byte operand in a general register or memory. The bit ...
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Instruction Descriptions The instructions are described starting in section 2.2.1. Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 41 of 258 REJ09B0213-0300 ...
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Section 2 Instruction Descriptions 2.2.1 (1) ADD (B) ADD (ADD binary) Operation Rd + (EAs) Rd Assembly-Language Format ADD.B <EAs>, Rd Operand Size Byte Description This instruction adds the source operand to the contents of an 8-bit register Rd (destination ...
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ADD (W) ADD (ADD binary) Operation Rd + (EAs) Rd Assembly-Language Format ADD.W <EAs>, Rd Operand Size Word Description This instruction adds the source operand to the contents of a 16-bit register Rd (destination operand) and stores the ...
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Section 2 Instruction Descriptions 2.2.1 (3) ADD (L) ADD (ADD binary) Operation ERd + (EAs) ERd Assembly-Language Format ADD.L <EAs>, ERd Operand Size Longword Description This instruction adds the source operand to the contents of a 32-bit register ERd (destination ...
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ADDS ADDS (ADD with Sign extension) Operation ERd ERd ERd Assembly-Language Format ADDS #1, ERd ADDS #2, ERd ADDS #4, ERd Operand Size Longword Description This instruction adds the immediate ...
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Section 2 Instruction Descriptions 2.2.3 ADDX ADDX (ADD with eXtend carry) Operation Rd + (EAs Assembly-Language Format ADDX <EAs>, Rd Operand Size Byte Description This instruction adds the source operand and carry flag to the contents of ...
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AND (B) AND (AND logical) Operation Rd (EAs) Rd Assembly-Language Format AND.B <EAs>, Rd Operand Size Byte Description This instruction ANDs the source operand with the contents of an 8-bit register Rd (destination register) and stores the result ...
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Section 2 Instruction Descriptions 2.2.4 (2) AND (W) AND (AND logical) Operation Rd (EAs) Rd Assembly-Language Format AND.W <EAs>, Rd Operand Size Word Description This instruction ANDs the source operand with the contents of a 16-bit register Rd (destination register) ...
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AND (L) AND (AND logical) Operation ERd (EAs) ERd Assembly-Language Format AND.L <EAs>, ERd Operand Size Longword Description This instruction ANDs the source operand with the contents of a 32-bit register ERd (destination register) and stores the result ...
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Section 2 Instruction Descriptions 2.2.5 ANDC ANDC (AND Control register) Operation CCR #IMM CCR Assembly-Language Format ANDC #xx:8, CCR Operand Size Byte Description This instruction ANDs the contents of the condition-code register (CCR) with immediate data and stores the result ...
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BAND BAND (Bit AND) Operation C (<bit No.> of <EAd>) Assembly-Language Format BAND #xx:3, <EAd> Operand Size Byte Description This instruction ANDs a specified bit in the destination operand with the carry bit and stores the result in the ...
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Section 2 Instruction Descriptions 2.2.7 Bcc Bcc (Branch conditionally) Operation If condition is true, then PC + disp PC else next; Assembly-Language Format Bcc disp Condition field Operand Size — Description If the condition specified in the condition field (cc) ...
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Bcc Bcc (Branch conditionally) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Program-counter BRA (BT) relative Program-counter BRN (BF) relative Program-counter BHI relative Program-counter BLS relative Program-counter Bcc (BHS) relative Program-counter BCS (BLO) relative Program-counter BNE ...
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Section 2 Instruction Descriptions 2.2.8 BCLR BCLR (Bit CLeaR) Operation 0 (<bit No.> of <EAd>) Assembly-Language Format BCLR #xx:3, <EAd> BCLR Rn, <EAd> Operand Size Byte Description This instruction clears a specified bit in the destination operand to 0. The ...
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BCLR BCLR (Bit CLeaR) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode * Register direct BCLR #xx:3, Rd Register indirect BCLR #xx:3, @ERd Absolute address BCLR #xx:3, @aa:8 Register direct BCLR Rn, Rd Register indirect BCLR ...
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Section 2 Instruction Descriptions 2.2.9 BIAND BIAND (Bit Invert AND) Operation C [¬ (<bit No.> of <EAd>)] Assembly-Language Format BIAND #xx:3, <EAd> Operand Size Byte Description This instruction ANDs the inverse of a specified bit in the destination operand with ...
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BILD BILD (Bit Invert LoaD) Operation ¬ (<bit No.> of <EAd>) C Assembly-Language Format BILD #xx:3, <EAd> Operand Size Byte Description This instruction loads the inverse of a specified bit from the destination operand into the carry bit. The ...
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Section 2 Instruction Descriptions 2.2.11 BIOR BIOR (Bit Invert inclusive OR) Operation C [¬ (<bit No.> of <EAd>)] Assembly-Language Format BIOR #xx:3, <EAd> Operand Size Byte Description This instruction ORs the inverse of a specified bit in the destination operand ...
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BIST BIST (Bit Invert STore) Operation ¬ C (<bit No.> of <EAd>) Assembly-Language Format BIST #xx:3, <EAd> Operand Size Byte Description This instruction stores the inverse of the carry bit in a specified bit location in the destination operand. ...
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Section 2 Instruction Descriptions 2.2.13 BIXOR BIXOR (Bit Invert eXclusive OR) Operation C [¬ (<bit No.> of <EAd>)] Assembly-Language Format BIXOR #xx:3, <EAd> Operand Size Byte Description This instruction exclusively ORs the inverse of a specified bit in the destination ...
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BLD BLD (Bit LoaD) Operation (<Bit No.> of <EAd>) C Assembly-Language Format BLD #xx:3, <EAd> Operand Size Byte Description This instruction loads a specified bit from the destination operand into the carry bit. The bit number is specified by ...
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Section 2 Instruction Descriptions 2.2.15 BNOT BNOT (Bit NOT) Operation ¬ (<bit No.> of <EAd>) (<bit No.> of <EAd>) Assembly-Language Format BNOT #xx:3, <EAd> BNOT Rn, <EAd> Operand Size Byte Description This instruction inverts a specified bit in the destination ...
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BNOT BNOT (Bit NOT) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode * Register direct BNOT #xx:3, Rd Register indirect BNOT #xx:3, @ERd Absolute address BNOT #xx:3, @aa:8 Register direct BNOT Rn, Rd Register indirect BNOT ...
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Section 2 Instruction Descriptions 2.2.16 BOR BOR (bit inclusive OR) Operation C [(<bit No.> of <EAd>)] Assembly-Language Format BOR #xx:3, <EAd> Operand Size Byte Description This instruction ORs a specified bit in the destination operand with the carry bit and ...
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BSET BSET (Bit SET) Operation 1 (<bit No.> of <EAd>) Assembly-Language Format BSET #xx:3, <EAd> BSET Rn, <EAd> Operand Size Byte Description This instruction sets a specified bit in the destination operand to 1. The bit number can be ...
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Section 2 Instruction Descriptions BSET BSET (Bit SET) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode * Register direct BSET #xx:3, Rd Register indirect BSET #xx:3, @ERd Absolute address BSET #xx:3, @aa:8 Register direct BSET Rn, ...
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BSR BSR (Branch to SubRoutine) Operation PC @– disp PC Assembly-Language Format BSR disp Operand Size — Description This instruction branches to a subroutine at a specified address. It pushes the program counter (PC) value onto the ...
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Section 2 Instruction Descriptions BSR BSR (Branch to SubRoutine) Notes The stack structure differs between normal mode and advanced mode. In normal mode only the lower 16 bits of the program counter are pushed on the stack ...
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BST BST (Bit STore) Operation C (<bit No.> of <EAd>) Assembly-Language Format BST #xx:3, <EAd> Operand Size Byte Description This instruction stores the carry bit in a specified bit location in the destination operand. The bit number is specified ...
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Section 2 Instruction Descriptions 2.2.20 BTST BTST (Bit TeST) Operation ¬ (<Bit No.> of <EAd>) Z Assembly-Language Format BTST #xx:3, <EAd> BTST Rn, <EAd> Operand Size Byte Description This instruction tests a specified bit in the destination operand and sets ...
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BTST BTST (Bit TeST) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode * Register direct BTST #xx:3, Rd Register indirect BTST #xx:3, @ERd Absolute address BTST #xx:3, @aa:8 Register direct BTST Rn, Rd Register indirect BTST ...
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Section 2 Instruction Descriptions 2.2.21 BXOR BXOR (Bit eXclusive OR) Operation C (<bit No.> of <EAd>) Assembly-Language Format BXOR #xx:3, <EAd> Operand Size Byte Description This instruction exclusively ORs a specified bit in the destination operand with the carry bit ...
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CMP (B) CMP (CoMPare) Operation Rd – (EAs), set or clear CCR Assembly-Language Format CMP.B <EAs>, Rd Operand Size Byte Description This instruction subtracts the source operand from the contents of an 8-bit register Rd (destination register) and ...
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Section 2 Instruction Descriptions 2.2.22 (2) CMP (W) CMP (CoMPare) Operation Rd – (EAs), set CCR Assembly-Language Format CMP.W <EAs>, Rd Operand Size Word Description This instruction subtracts the source operand from the contents of a 16-bit register Rd (destination ...
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CMP (L) CMP (CoMPare) Operation ERd – (EAs), set CCR Assembly-Language Format CMP.L <EAs>, ERd Operand Size Longword Description This instruction subtracts the source operand from the contents of a 32-bit register ERd (destination register) and sets or ...
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Section 2 Instruction Descriptions 2.2.23 DAA DAA (Decimal Adjust Add) Operation Rd (decimal adjust) Rd Assembly-Language Format DAA Rd Operand Size Byte Description Given that the result of an addition operation performed by an ADD.B or ADDX instruction on 4-bit ...
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DAA DAA (Decimal Adjust Add) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Register direct DAA Notes Valid results (8-bit register Rd contents and and H flags) are not assured if this ...
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Section 2 Instruction Descriptions 2.2.24 DAS DAS (Decimal Adjust Subtract) Operation Rd (decimal adjust) Rd Assembly-Language Format DAS Rd Operand Size Byte Description Given that the result of a subtraction operation performed by a SUB.B, SUBX.B, or NEG.B instruction on ...
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DAS DAS (Decimal Adjust Subtract) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Register direct DAS Notes Valid results (8-bit register Rd contents and and H flags) are not assured if this ...
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Section 2 Instruction Descriptions 2.2.25 (1) DEC (B) DEC (DECrement) Operation Rd – Assembly-Language Format DEC.B Rd Operand Size Byte Description This instruction decrements an 8-bit register Rd (destination register) and stores the result in the 8- bit ...
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DEC (W) DEC (DECrement) Operation Rd – – Assembly-Language Format DEC.W #1, Rd DEC.W #2, Rd Operand Size Word Description This instruction subtracts the immediate value from the contents of ...
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Section 2 Instruction Descriptions 2.2.25 (3) DEC (L) DEC (DECrement) Operation ERd – 1 ERd ERd – 2 ERd Assembly-Language Format DEC.L #1, ERd DEC.L #2, ERd Operand Size Longword Description This instruction subtracts the immediate value ...
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DIVXS (B) DIVXS (DIVide eXtend as Signed) Operation Rd ÷ Assembly-Language Format DIVXS.B Rs, Rd Operand Size Byte Description This instruction divides the contents of a 16-bit register Rd (destination register) by the contents of an ...
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Section 2 Instruction Descriptions DIVXS (B) DIVXS (DIVide eXtend as Signed) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Register direct DIVXS.B Notes The N flag is set the dividend and divisor have ...
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DIVXS (W) DIVXS (DIVide eXtend as Signed) Operation ERd ÷ Rs ERd Assembly-Language Format DIVXS.W Rs, ERd Operand Size Word Description This instruction divides the contents of a 32-bit register ERd (destination register) by the contents of a ...
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Section 2 Instruction Descriptions DIVXS (W) DIVXS (DIVide eXtend as Signed) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Register direct DIVXS.W Notes The N flag is set the dividend and divisor have ...
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DIVXS DIVXS (DIVide eXtend as Signed) DIVXS instruction, Division by Zero, and Overflow Since the DIVXS instruction does not detect division by zero or overflow, applications should detect and handle division by zero and overflow using techniques similar ...
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Section 2 Instruction Descriptions DIVXS DIVXS (DIVide eXtend as Signed) This program leaves a 16-bit quotient in R2 and an 8-bit remainder in R1H. R1 R1H R2 Example 2: Sign extend the 8-bit divisor to 16 bits, sign extend the ...
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DIVXS DIVXS (DIVide eXtend as Signed) 2. Programming solution for DIVXS.W R0, ER1 Example: Convert dividend and divisor to non-negative numbers, then use DIVXU programming solution for zero divide and overflow MOV.W R0, R0 BEQ ZERODIV ANDC #AF, CCR BPL ...
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Section 2 Instruction Descriptions DIVXS DIVXS (DIVide eXtend as Signed) This program leaves a 32-bit quotient in ER2 and a 16-bit remainder in E1. ER1 E1 ER2 The preceding two examples flag the status of the divisor and dividend in ...
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DIVXU (B) DIVXU (DIVide eXtend as Unsigned) Operation Rd ÷ Assembly-Language Format DIVXU.B Rs, Rd Operand Size Byte Description This instruction divides the contents of a 16-bit register Rd (destination register) by the contents of an ...
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Section 2 Instruction Descriptions 2.2.27 (2) DIVXU (W) DIVXU (DIVide eXtend as Unsigned) Operation ERd ÷ Rs ERd Assembly-Language Format DIVXU.W Rs, ERd Operand Size Word Description This instruction divides the contents of a 32-bit register ERd (destination register) by ...
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DIVXU DIVXU (DIVide eXtend as Unsigned) DIVXU Instruction, Zero Divide, and Overflow Zero divide and overflow are not detected in the DIVXU instruction. A program like the following can detect zero divisors and avoid overflow. 1. Programming solutions for DIVXU.B ...
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Section 2 Instruction Descriptions DIVXU DIVXU (DIVide eXtend as Unsigned) The resulting operation is 16 bits ÷ 8 bits overflow occurs. The 16-bit quotient is stored in R2, the 8-bit remainder in R1H ...
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DIVXU DIVXU (DIVide eXtend as Unsigned) Example 2: Zero-extend divisor from bits and dividend from bits before dividing EXTU.W R0 BEQ ZERODIV EXTU.L ER1 EXTU.W R0, ER1 RTS ZERODIV: Instead of 16 bits ÷ ...
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Section 2 Instruction Descriptions DIVXU DIVXU (DIVide eXtend as Unsigned) 2. Programming solution for DIVXU.W R0, ER1 Example 1: Divide upper 16 bits and lower 16 bits of 32-bit dividend separately and obtain 32-bit quotient MOV.W R0, R0 BEQ ZERODIV ...
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EEPMOV (B) EEPMOV (MOVe data to EEPROM) Operation if R4L 0 then repeat @ER5+ R4L – 1 until R4L = 0 else next; Assembly-Language Format EEPMOV.B Operand Size — Description This instruction performs a block memory transfer. It ...
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Section 2 Instruction Descriptions 2.2.28 (2) EEPMOV (W) EEPMOV (MOVe data to EEPROM) Operation then repeat @ER5+ R4 – until else next; Assembly-Language Format EEPMOV.W Operand Size — Description This instruction performs ...
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EEPMOV (W) EEPMOV (MOVe data to EEPROM) EEPMOV.W Instruction and NMI Interrupt If an NMI request occurs while the EEPMOV.W instruction is being executed, NMI interrupt exception handling is carried out at the end of the current read-write cycle. Register ...
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Section 2 Instruction Descriptions 2.2.29 (1) EXTS (W) EXTS (EXTend as Signed) Operation (<Bit 7> of Rd) (<bits 15 to 8> of Rd> Assembly-Language Format EXTS.W Rd Operand Size Word Description This instruction copies the sign of the lower 8 ...
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EXTS (L) EXTS (EXTend as Signed) Operation (<Bit 15> of ERd) (<bits 31 to 16> of ERd>) Assembly-Language Format EXTS.L ERd Operand Size Longword Description This instruction copies the sign of the lower 16 bits (general register Rd) ...
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Section 2 Instruction Descriptions 2.2.30 (1) EXTU (W) EXTU (EXTend as Unsigned) Operation 0 (<bits 15 to 8> of Rd>) Zero extend Assembly-Language Format EXTU.W Rd Operand Size Word Description This instruction extends the lower 8 bits in a 16-bit ...
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EXTU (L) EXTU (EXTend as Unsigned) Operation 0 (<bits 31 to 16> of ERd>) Zero extend Assembly-Language Format EXTU.L ERd Operand Size Longword Description This instruction extends the lower 16 bits (general register Rd 32-bit register ...
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Section 2 Instruction Descriptions 2.2.31 (1) INC (B) INC (INCrement) Operation Assembly-Language Format INC.B Rd Operand Size Byte Description This instruction increments an 8-bit register Rd (destination register) and stores the result in the 8-bit register ...
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INC (W) INC (INCrement) Operation Assembly-Language Format INC.W #1, Rd INC.W #2, Rd Operand Size Word Description This instruction adds the immediate value the contents of ...
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Section 2 Instruction Descriptions 2.2.31 (3) INC (L) INC (INCrement) Operation ERd + 1 ERd ERd + 2 ERd Assembly-Language Format INC.L #1, ERd INC.L #2, ERd Operand Size Longword Description This instruction adds the immediate value ...
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JMP JMP (JuMP) Operation Effective address PC Assembly-Language Format JMP <EA> Operand Size — Description This instruction branches unconditionally to a specified address Available Registers ERn: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing ...
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Section 2 Instruction Descriptions 2.2.33 JSR JSR (Jump to SubRoutine) Operation PC @–SP Effective address PC Assembly-Language Format JSR <EA> Operand Size — Description This instruction pushes the program counter on the stack as a return address, then branches to ...
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JSR JSR (Jump to SubRoutine) Notes Note that the structures of the stack and branch addresses differ between normal and advanced mode. Only the lower 16 bits of the PC are saved in normal mode. The branch address must be ...
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Section 2 Instruction Descriptions 2.2.34 (1) LDC (B) LDC (LoaD to Control register) Operation (EAs) CCR Assembly-Language Format LDC.B <EAs>, CCR Operand Size Byte Description This instruction loads the source operand into the CCR. Note that no interrupts, even NMI ...
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LDC (W) LDC (LoaD to Control register) Operation (EAs) CCR Assembly-Language Format LDC.W <EAs>, CCR Operand Size Word Description This instruction loads the source operand contents into the condition-code register (CCR). Although CCR is a byte register, the ...
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Section 2 Instruction Descriptions LDC (W) LDC (LoaD to Control register) Rev. 3.00 Dec 13, 2004 page 112 of 258 REJ09B0213-0300 Load CCR ...
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MOV (B) MOV (MOVe data) Operation Rs Rd Assembly-Language Format MOV.B Rs, Rd Operand Size Byte Description This instruction transfers one byte of data from an 8-bit register 8-bit register Rd, tests the transferred data, ...
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Section 2 Instruction Descriptions 2.2.35 (2) MOV (W) MOV (MOVe data) Operation Rs Rd Assembly-Language Format MOV.W Rs, Rd Operand Size Word Description This instruction transfers one word of data from a 16-bit register 16-bit register Rd, ...
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MOV (L) MOV (MOVe data) Operation ERs ERd Assembly-Language Format MOV.L ERs, ERd Operand Size Longword Description This instruction transfers one longword of data from a 32-bit register ERs to a 32-bit register ERd, tests the transferred data, ...
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Section 2 Instruction Descriptions 2.2.35 (4) MOV (B) MOV (MOVe data) Operation (EAs) Rd Assembly-Language Format MOV.B <EAs>, Rd Operand Size Byte Description This instruction transfers the source operand contents to an 8-bit register Rs, tests the transferred data, and ...
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MOV (B) MOV (MOVe data) Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 117 of 258 REJ09B0213-0300 Move ...
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Section 2 Instruction Descriptions 2.2.35 (5) MOV (W) MOV (MOVe data) Operation (EAs) Rd Assembly-Language Format MOV.W <EAs>, Rd Operand Size Word Description This instruction transfers the source operand contents to a 16-bit register Rd, tests the transferred data, and ...
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MOV (W) MOV (MOVe data) Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 119 of 258 REJ09B0213-0300 Move ...
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Section 2 Instruction Descriptions 2.2.35 (6) MOV (L) MOV (MOVe data) Operation (EAs) ERd Assembly-Language Format MOV.L <EAs>, ERd Operand Size Longword Description This instruction transfers the source operand contents to a specified 32-bit register (ERd), tests the transferred data, ...
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MOV (L) MOV (MOVe data) Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 121 of 258 REJ09B0213-0300 Move ...
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Section 2 Instruction Descriptions 2.2.35 (7) MOV (B) MOV (MOVe data) Operation Rs (EAd) Assembly-Language Format MOV.B Rs, <EAd> Operand Size Byte Description This instruction transfers the contents of an 8-bit register Rs (source operand destination location, tests ...
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MOV (B) MOV (MOVe data) Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 123 of 258 REJ09B0213-0300 Move ...
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Section 2 Instruction Descriptions 2.2.35 (8) MOV (W) MOV (MOVe data) Operation Rs (EAd) Assembly-Language Format MOV.W Rs, <EAd> Operand Size Word Description This instruction transfers the contents of a 16-bit register Rs (source operand destination location, tests ...
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MOV (W) MOV (MOVe data) Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 125 of 258 REJ09B0213-0300 Move ...
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Section 2 Instruction Descriptions 2.2.35 (9) MOV (L) MOV (MOVe data) Operation ERs (EAd) Assembly-Language Format MOV.L ERs, <EAd> Operand Size Longword Description This instruction transfers the contents of a 32-bit register ERs (source operand destination location, tests ...
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MOV (L) MOV (MOVe data) Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 127 of 258 REJ09B0213-0300 Move ...
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Section 2 Instruction Descriptions 2.2.36 MOVFPE MOVFPE (MOVe From Peripheral with E clock) Operation (EAs) Rd Synchronized with E clock Assembly-Language Format MOVFPE @aa:16, Rd Operand Size Byte Description This instruction transfers memory contents specified by a 16-bit absolute address ...
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MOVTPE MOVTPE (MOVe To Peripheral with E clock) Operation Rs (EAd) Synchronized with E clock Assembly-Language Format MOVTPE Rs, @aa:16 Operand Size Byte Description This instruction transfers the contents of a general register Rs (source operand destination ...
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Section 2 Instruction Descriptions 2.2.38 (1) MULXS (B) MULXS (MULtiply eXtend as Signed) Operation Assembly-Language Format MULXS.B Rs, Rd Operand Size Byte Description This instruction multiplies the lower 8 bits of a 16-bit register Rd (destination operand) ...
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MULXS (W) MULXS (MULtiply eXtend as Signed) Operation ERd Rs ERd Assembly-Language Format MULXS.W Rs, ERd Operand Size Word Description This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination operand) by the contents of ...
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Section 2 Instruction Descriptions 2.2.39 (1) MULXU (B) MULXU (MULtiply eXtend as Unsigned) Operation Assembly-Language Format MULXU.B Rs, Rd Operand Size Byte Description This instruction multiplies the lower 8 bits of a 16-bit register Rd (destination operand) ...
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MULXU (W) MULXU (MULtiply eXtend as Unsigned) Operation ERd Rs ERd Assembly-Language Format MULXU.W Rs, ERd Operand Size Word Description This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination operand) by the contents of ...
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Section 2 Instruction Descriptions 2.2.40 (1) NEG (B) NEG (NEGate) Operation 0 – Assembly-Language Format NEG.B Rd Operand Size Byte Description This instruction takes the two’s complement of the contents of an 8-bit register Rd (destination operand) and ...
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NEG (W) NEG (NEGate) Operation 0 – Assembly-Language Format NEG.W Rd Operand Size Word Description This instruction takes the two’s complement of the contents of a 16-bit register Rd (destination operand) and stores the result in ...
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Section 2 Instruction Descriptions 2.2.40 (3) NEG (L) NEG (NEGate) Operation 0 – ERd ERd Assembly-Language Format NEG.L ERd Operand Size Longword Description This instruction takes the two’s complement of the contents of a 32-bit register ERd (destination operand) and ...
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NOP NOP (No OPeration) Operation Assembly-Language Format NOP Operand Size — Description This instruction only increments the program counter, causing the next instruction to be executed. The internal state of the CPU does not change. ...
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Section 2 Instruction Descriptions 2.2.42 (1) NOT (B) NOT (NOT = logical complement) Operation Rd Rd Assembly-Language Format NOT.B Rd Operand Size Byte Description This instruction takes the one’s complement of the contents of an 8-bit register Rd (destination operand) ...
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NOT (W) NOT (NOT = logical complement) Operation Rd Rd Assembly-Language Format NOT.W Rd Operand Size Word Description This instruction takes the one’s complement of the contents of a 16-bit register Rd (destination operand) and stores the result ...
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Section 2 Instruction Descriptions 2.2.42 (3) NOT (L) NOT (NOT = logical complement) Operation ERd ERd Assembly-Language Format NOT.L ERd Operand Size Longword Description This instruction takes the one’s complement of the contents of a 32-bit register ERd (destination operand) ...
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OR (B) OR (inclusive OR logical) Operation Rd (EAs) Rd Assembly-Language Format OR.B <EAs>, Rd Operand Size Byte Description This instruction ORs the source operand with the contents of an 8-bit register Rd (destination register) and stores the ...
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Section 2 Instruction Descriptions 2.2.43 (2) OR (W) OR (inclusive OR logical) Operation Rd (EAs) Rd Assembly-Language Format OR.W <EAs>, Rd Operand Size Word Description This instruction ORs the source operand with the contents of a 16-bit register Rd (destination ...
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OR (L) OR (inclusive OR logical) Operation ERd (EAs) ERd Assembly-Language Format OR.L <EAs>, ERd Operand Size Longword Description This instruction ORs the source operand with the contents of a 32-bit register ERd (destination register) and stores the ...
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Section 2 Instruction Descriptions 2.2.44 ORC ORC (inclusive OR Control register) Operation CCR #IMM CCR Assembly-Language Format ORC #xx:8, CCR Operand Size Byte Description This instruction ORs the contents of the condition-code register (CCR) with immediate data and stores the ...
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POP (W) POP (POP data) Operation @SP+ Rn Assembly-Language Format POP.W Rn Operand Size Word Description This instruction restores data from the stack to a 16-bit general register Rn, tests the restored data, and sets condition-code flags according ...
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Section 2 Instruction Descriptions 2.2.45 (2) POP (L) POP (POP data) Operation @SP+ ERn Assembly-Language Format POP.L ERn Operand Size Longword Description This instruction restores data from the stack to a 32-bit general register ERn, tests the restored data, and ...
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PUSH (W) PUSH (PUSH data) Operation Rn @–SP Assembly-Language Format PUSH.W Rn Operand Size Word Description This instruction saves data from a 16-bit register Rn onto the stack, tests the saved data, and sets condition-code flags according to ...
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Section 2 Instruction Descriptions 2.2.46 (2) PUSH (L) PUSH (PUSH data) Operation ERn @–SP Assembly-Language Format PUSH.L ERn Operand Size Longword Description This instruction pushes data from a 32-bit register ERn onto the stack, tests the saved data, and sets ...
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ROTL (B) ROTL (ROTate Left) Operation Rd (left rotation) Rd Assembly-Language Format ROTL.B Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination register) one bit to the left. The most significant ...
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Section 2 Instruction Descriptions 2.2.47 (2) ROTL (W) ROTL (ROTate Left) Operation Rd (left rotation) Rd Assembly-Language Format ROTL.W Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination register) one bit to the ...
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ROTL (L) ROTL (ROTate Left) Operation ERd (left rotation) ERd Assembly-Language Format ROTL.L ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination register) one bit to the left. The most significant ...
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Section 2 Instruction Descriptions 2.2.48 (1) ROTR (B) ROTR (ROTate Right) Operation Rd (right rotation) Rd Assembly-Language Format ROTR.B Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination register) one bit to the ...
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ROTR (W) ROTR (ROTate Right) Operation Rd (right rotation) Rd Assembly-Language Format ROTR.W Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination register) one bit to the right. The least significant ...
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Section 2 Instruction Descriptions 2.2.48 (3) ROTR (L) ROTR (ROTate Right) Operation ERd (right rotation) ERd Assembly-Language Format ROTR.L ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination register) one bit to the ...
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ROTXL (B) ROTXL (ROTate with eXtend carry Left) Operation Rd (left rotation through carry bit) Assembly-Language Format ROTXL.B Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination register) one bit to ...
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Section 2 Instruction Descriptions 2.2.49 (2) ROTXL (W) ROTXL (ROTate with eXtend carry Left) Operation Rd (left rotation through carry bit) Assembly-Language Format ROTXL.W Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination ...
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ROTXL (L) ROTXL (ROTate with eXtend carry Left) Operation ERd (left rotation through carry bit) Assembly-Language Format ROTXL.L ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination register) one bit to ...
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Section 2 Instruction Descriptions 2.2.50 (1) ROTXR (B) ROTXR (ROTate with eXtend carry Right) Operation Rd (right rotation through carry bit) Assembly-Language Format ROTXR.B Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination ...
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ROTXR (W) ROTXR (ROTate with eXtend carry Right) Operation Rd (right rotation through carry bit) Assembly-Language Format ROTXR.W Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination register) one bit to ...
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Section 2 Instruction Descriptions 2.2.50 (3) ROTXR (L) ROTXR (ROTate with eXtend carry Right) Operation ERd (right rotation through carry bit) Assembly-Language Format ROTXR.L ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination ...
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RTE RTE (ReTurn from Exception) Operation @SP+ CCR @SP+ PC Assembly-Language Format RTE Operand Size — Description This instruction returns from an exception-handling routine by restoring the condition-code register (CCR) and program counter (PC) from the stack. Program execution ...
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Section 2 Instruction Descriptions RTE RTE (ReTurn from Exception) Notes The stack structure differs between normal mode and advanced mode. Don’t care PC Undet. Normal mode Rev. 3.00 Dec 13, 2004 page 162 of 258 REJ09B0213-0300 CCR ...
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RTS RTS (ReTurn from Subroutine) Operation @SP+ PC Assembly-Language Format RTS Operand Size — Description This instruction returns from a subroutine by restoring the program counter (PC) from the stack. Program execution continues from the address restored to the ...
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Section 2 Instruction Descriptions 2.2.53 (1) SHAL (B) SHAL (SHift Arithmetic Left) Operation Rd (left arithmetic shift) Rd Assembly-Language Format SHAL.B Rd Operand Size Byte Description This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit ...
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SHAL (W) SHAL (SHift Arithmetic Left) Operation Rd (left arithmetic shift) Rd Assembly-Language Format SHAL.W Rd Operand Size Word Description This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the left. The ...
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Section 2 Instruction Descriptions 2.2.53 (3) SHAL (L) SHAL (SHift Arithmetic Left) Operation ERd (left arithmetic shift) ERd Assembly-Language Format SHAL.L ERd Operand Size Longword Description This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit ...
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SHAR (B) SHAR (SHift Arithmetic Right) Operation Rd (right arithmetic shift) Rd Assembly-Language Format SHAR.B Rd Operand Size Byte Description This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the right. Bit ...
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Section 2 Instruction Descriptions 2.2.54 (2) SHAR (W) SHAR (SHift Arithmetic Right) Operation Rd (right arithmetic shift) Rd Assembly-Language Format SHAR.W Rd Operand Size Word Description This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit ...
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SHAR (L) SHAR (SHift Arithmetic Right) Operation ERd (right arithmetic shift) Assembly-Language Format SHAR.L ERd Operand Size Longword Description This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the right. Bit 0 ...
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Section 2 Instruction Descriptions 2.2.55 (1) SHLL (B) SHLL (SHift Logical Left) Operation Rd (left logical shift) Rd Assembly-Language Format SHLL.B Rd Operand Size Byte Description This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit ...
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SHLL (W) SHLL (SHift Logical Left) Operation Rd (left logical shift) Rd Assembly-Language Format SHLL.W Rd Operand Size Word Description This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the left. The ...
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Section 2 Instruction Descriptions 2.2.55 (3) SHLL (L) SHLL (SHift Logical Left) Operation ERd (left logical shift) ERd Assembly-Language Format SHLL.L ERd Operand Size Longword Description This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit ...
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SHLR (B) SHLR (SHift Logical Right) Operation Rd (right logical shift) Rd Assembly-Language Format SHLR.B Rd Operand Size Byte Description This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the right. The ...
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Section 2 Instruction Descriptions 2.2.56 (2) SHLR (W) SHLR (SHift Logical Right) Operation Rd (right logical shift) Rd Assembly-Language Format SHLR.W Rd Operand Size Word Description This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit ...
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SHLR (L) SHLR (SHift Logical Right) Operation ERd (right logical shift) ERd Assembly-Language Format SHLR.L ERd Operand Size Longword Description This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the right. The ...
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Section 2 Instruction Descriptions 2.2.57 SLEEP SLEEP (SLEEP) Operation Program execution state power-down mode Assembly-Language Format SLEEP Operand Size — Description When the SLEEP instruction is executed, the CPU enters a power-down state. Its internal state remains unchanged, but the ...
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STC (B) STC (STore from Control register) Operation CCR Rd Assembly-Language Format STC.B CCR, Rd Operand Size Byte Description This instruction copies the CCR contents to an 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to ...
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Section 2 Instruction Descriptions 2.2.58 (2) STC (W) STC (STore from Control register) Operation CCR (EAd) Assembly-Language Format STC.W CCR, <EAd> Operand Size Word Description This instruction copies the CCR contents to a destination location. Although CCR is a byte ...
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STC (W) STC (STore from Control register) Section 2 Instruction Descriptions Store CCR Rev. 3.00 Dec 13, 2004 page 179 of 258 REJ09B0213-0300 ...
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Section 2 Instruction Descriptions 2.2.59 (1) SUB (B) SUB (SUBtract binary) Operation Rd – Assembly-Language Format SUB.B Rs, Rd Operand Size Byte Description This instruction subtracts the contents of an 8-bit register Rs (source operand) from the contents ...
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SUB (B) SUB (SUBtract binary) Notes The SUB.B instruction can operate only on general registers. Immediate data can be subtracted from general register contents by using the SUBX instruction. Before executing SUBX #xx:8, Rd, first set the Z flag to ...
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Section 2 Instruction Descriptions 2.2.59 (2) SUB (W) SUB (SUBtract binary) Operation Rd – (EAs) Rd Assembly-Language Format SUB.W <EAs>, Rd Operand Size Word Description This instruction subtracts a source operand from the contents of a 16-bit register Rd (destination ...
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SUB (L) SUB (SUBtract binary) Operation ERd – <EAs> ERd Assembly-Language Format SUB.L <EAs>, ERd Operand Size Longword Description This instruction subtracts a source operand from the contents of a 32-bit register ERd (destination operand) and stores the ...
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Section 2 Instruction Descriptions 2.2.60 SUBS SUBS (SUBtract with Sign extension) Operation ERd – 1 ERd ERd – 2 ERd ERd – 4 ERd Assembly-Language Format SUBS #1, ERd SUBS #2, ERd SUBS #4, ERd Operand Size Longword Description This ...