HD64F3672FPV Renesas Electronics America, HD64F3672FPV Datasheet - Page 181

IC H8/3672 MCU FLASH 64LQFP

HD64F3672FPV

Manufacturer Part Number
HD64F3672FPV
Description
IC H8/3672 MCU FLASH 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheets

Specifications of HD64F3672FPV

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
26
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3672FPV
Manufacturer:
MICROCHIP
Quantity:
1 000
Part Number:
HD64F3672FPV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
HD64F3672FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3672FPV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
2.2.53 (2) SHAL (W)
Notes
The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag.
SHAL (SHift Arithmetic Left)
Operation
Rd (left arithmetic shift)
Assembly-Language Format
SHAL.W Rd
Operand Size
Word
Description
This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the left. The
most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Register direct
Addressing
Mode
Mnemonic
SHAL.W
C
Rd
MSB
Operands
b
15
Rd
1st byte
. . . . . .
1
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Receives the previous value in bit 15.
2nd byte
9
cleared to 0.
cleared to 0.
cleared to 0.
Instruction Format
— —
Rev. 3.00 Dec 13, 2004 page 165 of 258
I
rd
UI
Section 2 Instruction Descriptions
— —
H
3rd byte
LSB
b
0
U
N
0
4th byte
REJ09B0213-0300
Shift Arithmetic
Z
V
States
No. of
C
2

Related parts for HD64F3672FPV