HD64F3672FPV Renesas Electronics America, HD64F3672FPV Datasheet - Page 27
HD64F3672FPV
Manufacturer Part Number
HD64F3672FPV
Description
IC H8/3672 MCU FLASH 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheets
1.DF36912GFHV.pdf
(277 pages)
2.DF36012GFYV.pdf
(1021 pages)
3.HD64F3672FXV.pdf
(334 pages)
Specifications of HD64F3672FPV
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
26
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instructions.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero
result.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions
leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits,
refer to the detailed descriptions of the instructions starting in section 2.2.1.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
1.4.4
When the CPU is reset, the program counter (PC) is loaded from the vector table and the I bit in
the condition-code register (CCR) is set to 1. The other CCR bits and the general registers and
extended registers are not initialized. In particular, the stack pointer (extended register E7 and
general register R7) is not initialized. The stack pointer must therefore be initialized by an MOV.L
instruction executed immediately after a reset.
Add instructions, to indicate a carry
Subtract instructions, to indicate a borrow
Shift and rotate instructions, to store the value shifted out of the end bit
Initial Register Values
Rev. 3.00 Dec 13, 2004 page 11 of 258
REJ09B0213-0300
Section 1 CPU
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