M30263F6AFP#U5 Renesas Electronics America, M30263F6AFP#U5 Datasheet - Page 133
![MCU 3/5V 48K PB-FREE 42-SSOP](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U5
Manufacturer Part Number
M30263F6AFP#U5
Description
MCU 3/5V 48K PB-FREE 42-SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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1
Figure 12.2.3.3 Operation timing when measuring a pulse width
Figure 12.2.3.2 Operation timing when measuring a pulse period
0
6
2
9
C
0 .
B
NOTES:
i = 0 to 2
0
2 /
0
Measurement pulse
Timing at which counter
reaches “0000
TBiS bit
IR bit in the TBiIC
register
MR3 bit in theTBiMR
register
Reload register
transfer timing
NOTES:
2
i = 0 to 2
6
TBiS bit
IR bit in the TBiIC
register
MR3 bit in the TBiMR
register
Count source
Measurement pulse
Reload register
transfer timing
Timing at which counter
reaches “0000
0
F
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “00
A
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “10
2
e
from falling edge to falling edge of the measurement pulse).
0 -
b
interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of
the measurement pulse).
G
1 .
2
o r
Count source
0
, 5
0
u
2
p
0
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
16
(
0
M
”
16
7
”
counter
1
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
counter
6
page 114
C
2 /
“H”
“L”
“1”
“0”
“1”
“0”
“1”
“0”
“H”
“0”
“1”
“0”
“1”
“0”
“1”
6
“L”
, A
M
f o
1
6
3
C
2
9
2 /
Set to “0” upon accepting an interrupt request or by writing in
program
6
, B
Set to “0” upon accepting an interrupt request or by
writing in program
M
1
Transfer
(indeterminate
value)
6
(1)
C
2 /
6
) T
Transfer
(indeterminate value)
Transfer
(measured value)
(1)
(1)
Transfer
(measured
value)
(1)
Transfer
(measured value)
Transfer
(measured value)
(1)
(1)
2
2
” (measure the interval
” (measure the
(2)
(2)
12. Timer
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