M30263F6AFP#U5 Renesas Electronics America, M30263F6AFP#U5 Datasheet - Page 89
![MCU 3/5V 48K PB-FREE 42-SSOP](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U5
Manufacturer Part Number
M30263F6AFP#U5
Description
MCU 3/5V 48K PB-FREE 42-SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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e
E
9.4 Interrupt Sequence
1
. v
J
Figure 9.4.1. Time Required for Executing Interrupt Sequence
6
0
2
C
An interrupt sequence (the devicebehavior from the instant an interrupt is accepted to the instant the inter-
rupt routine is executed) is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
The CPU behavior during the interrupt sequence is described below. Figure 9.4.1 shows time required for
executing the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal
(3) The I, D and U flags in the FLG register become as follows:
(4) The CPU’s internal temporary register
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
NOTE:
9
0 .
B
2 /
Address bus
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
0
0
the address 00000
requested).
temporary register
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
1. This register cannot be used by user.
CPU clock
6
2
Data bus
A
0
F
2
e
G
0 -
WR
b
RD
o r
1 .
2
0
, 5
(2)
(2)
u
0
p
2
0
(
M
0
NOTES:
7
1
6
1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the
2. RD is the internal signal which is set to “L” when the internal memory is read out and WR is the
1
C
internal signal which is set to “L” when the internal memory is written.
instruction queue buffer is ready to accept instructions.
page 70
2 /
Address
0000
(1)
16
6
information
2
Interrupt
, A
.
. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not
16
M
3
1
f o
6
C
3
2
4
2 /
9
6
Indeterminate
, B
Indeterminate
5
Indeterminate
M
1
6
6
(1)
C
2 /
is saved to the stack.
7
6
(1)
(1)
) T
(1)
8
SP-2
9
contents
SP-2
10
SP-4
11
contents
SP-4
12
13
vec
contents
vec
14
vec+2
15
contents
vec+2
16
17
PC
18
9. Interrupt
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