M30263F6AFP#U5 Renesas Electronics America, M30263F6AFP#U5 Datasheet - Page 97
![MCU 3/5V 48K PB-FREE 42-SSOP](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U5
Manufacturer Part Number
M30263F6AFP#U5
Description
MCU 3/5V 48K PB-FREE 42-SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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9.9 Address Match Interrupt
1
. v
J
Table 9.9.1. Value of the PC that is saved to the stack area when an address match interrupt
Table 9.9.2. Relationship Between Address Match Interrupt Sources and Associated Registers
Value of the PC that is saved to the stack area : Refer to “Saving Registers”.
Op-code is an abbreviation of Operation Code. It is a portion of instruction code.
Refer to Chapter 4 Instruction Code/Number of Cycles in M16C/60, M16C/20 Series Software Manual. Op-code is shown
as a bold-framed figure directly below the Syntax.
6
0
Address match interrupt 0
Address match interrupt 1
• 2-byte op-code instruction
• 1-byte op-code instructions which are followed:
Instructions other than the above
2
C
An address match interrupt request is generated immediately before executing the instruction at the ad-
dress indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi
register. Use the AIER register’s AIER0 and AIER1 bits to enable or disable the interrupt. Note that the
address match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the
PC that is saved to the stack area varies depending on the instruction being executed (refer to “Saving
Registers”).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one
of the methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 9.9.1 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Figure 9.9.1 shows the AIER, RMAD0 and RMAD1 registers.
Address match interrupt sources Address match interrupt enable bit
9
0 .
B
2 /
ADD.B:S
OR.B:S
STNZ.B
CMP.B:S
JMPS
MOV.B:S
0
0
6
2
A
0
F
2
e
G
0 -
b
o r
1 .
2
0
, 5
u
0
p
2
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8
#IMM,dest (However, dest=A0 or A1)
0
(
Instruction at the address indicated by the RMADi register
request is accepted.
M
0
7
1
6
C
page 78
2 /
6
, A
SUB.B:S
MOV.B:S
STZX.B
PUSHM
JSRS
M
1
f o
6
C
3
2
2 /
9
6
AIER0
AIER1
, B
#IMM8,dest
#IMM8,dest
#IMM81,#IMM82,dest
src
#IMM8
M
1
6
C
2 /
6
) T
AND.B:S
STZ.B
POPM dest
#IMM8,dest
#IMM8,dest
RMAD0
RMAD1
Address match interrupt register
Value of the PC that is
saved to the stack area
The address
indicated by the
RMADi register +2
The address
indicated by the
RMADi register +1
9. Interrupt
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