M30263F6AFP#U5 Renesas Electronics America, M30263F6AFP#U5 Datasheet - Page 182
![MCU 3/5V 48K PB-FREE 42-SSOP](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U5
Manufacturer Part Number
M30263F6AFP#U5
Description
MCU 3/5V 48K PB-FREE 42-SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
R
M
e
E
1
. v
J
6
Figure 13.1.3.2. Transfer to U2RB Register and Interrupt Timing
0
C
2
9
0 .
B
2 /
0
0
6
(1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay)
(3) When the IICM2 bit is set to "1" (UART transmit or receive interrupt) and the CKPH bit is set to "0"
2
(2) When the IICM2 bit is set to "0" and the CKPH bit is set to "1" (clock delay)
SCL2
SDA2
SCL2
SDA2
SCL2
SDA2
SCL2
SDA2
A
(4) When the IICM2 bit is set to "1" and the CKPH bit is set to "1"
0
F
2
e
The above timing applies to the following setting :
• The CKDIR bit in the U2MR register is set to "1" (slave)
G
0 -
b
o r
1 .
2
0
, 5
u
0
p
2
(
0
1st
1st
1st
M
bit
bit
bit
1st
bit
0
D
D
D
D
7
1
7
7
7
7
6
C
page 163
2nd
2nd
2nd
bit
2nd
bit
bit
2 /
bit
D
D
D
D
6
6
6
6
6
, A
3rd
3rd
3rd
bit
3rd
bit
bit
M
bit
D
D
D
D
1
5
5
5
f o
5
6
C
3
4th
4th
4th
bit
bit
bit
4th
Data is transferred to the U2RB register
bit
2
2 /
D
D
Data is transferred to the U2RB register
D
D
9
4
4
4
6
b15
4
, B
•••
5th
5th
5th
bit
bit
bit
5th
bit
M
D
D
D
b9
D
Contents of the U2RB register
3
3
3
1
3
D
b8
6
0
C
6th
6th
6th
bit
bit
bit
6th
b7
bit
D
2 /
D
D
D
D
Data is transferred to the U2RB register
2
2
2
Data is transferred to the U2RB register
2
6
7
Receive interrupt
(DMA request)
D
) T
Receive interrupt
(DMA request)
6
7th
7th
7th
bit
bit
bit
7th
bit
D
D
D
D
D
5
1
1
1
D
1
4
D
8th
8th
8th
bit
bit
bit
8th
3
bit
ACK interrupt (DMA
request) or NACK interrupt
ACK interrupt (DMA
request) or NACK interrupt
D
D
D
D
D
0
2
0
0
0
D
b0
1
9th
bit
9th
9th
bit
bit
9th
D
bit
D
D
D
8
8
8
Transmit interrupt
b15
b15
8
Data is transferred to the U2RB register
(ACK or NACK)
(ACK or NACK)
(ACK or NACK)
(ACK or NACK)
Transmit interrupt
•••
•••
b9
b9
Contents of the U2RB register
Contents of the U2RB register
D
D
b8
b8
8
0
D
b7
b7
7
D
D
6
7
b15
D
D
5
6
•••
•••
D
D
4
5
b15
Contents of the U2RB register
Contents of the U2RB register
D
b9
D
3
4
D
D
D
b8
D
8
8
2
3
b9
D
D
D
b7
D
7
7
1
2
D
D
b8
D
D
b0
b0
6
6
0
1
D
D
b7
5
5
D
D
4
4
D
D
3
3
D
D
13. Serial I/O
2
2
D
D
1
1
D
D
b0
b0
0
0
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