DF2212CUNP24V Renesas Electronics America, DF2212CUNP24V Datasheet - Page 340
![MCU 16BIT FLASH 3V 128K 64-QFN](/photos/28/61/286186/64-vfqfn_sml.jpg)
DF2212CUNP24V
Manufacturer Part Number
DF2212CUNP24V
Description
MCU 16BIT FLASH 3V 128K 64-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2218UTF24V.pdf
(758 pages)
Specifications of DF2212CUNP24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2212CUNP24V
Manufacturer:
Renesas Electronics America
Quantity:
135
- Current page: 340 of 758
- Download datasheet (5Mb)
9.3.3
The TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for
channels 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the
TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST
bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the
counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this
setting is invalid and the register operates as a buffer register.
• TIORH_0, TIOR_1, TIOR_2
• TIORL_0
Rev.7.00 Dec. 24, 2008 Page 284 of 698
REJ09B0074-0700
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name Initial value
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
Bit Name Initial value
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
Timer I/O Control Register (TIOR)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
I/O Control B3 to B0
Specify the function of TGRB.
I/O Control A3 to A0
Specify the function of TGRA.
Description
I/O Control D3 to D0
Specify the function of TGRD.
I/O Control C3 to C0
Specify the function of TGRC.
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