DF2212CUNP24V Renesas Electronics America, DF2212CUNP24V Datasheet - Page 679
![MCU 16BIT FLASH 3V 128K 64-QFN](/photos/28/61/286186/64-vfqfn_sml.jpg)
DF2212CUNP24V
Manufacturer Part Number
DF2212CUNP24V
Description
MCU 16BIT FLASH 3V 128K 64-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2218UTF24V.pdf
(758 pages)
Specifications of DF2212CUNP24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2212CUNP24V
Manufacturer:
Renesas Electronics America
Quantity:
135
- Current page: 679 of 758
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Timing of Recovery from Hardware Standby Mode:
Drive the RES signal low approximately 100 ns or more before STBY goes high to execute a
power-on reset.
20.6
Module stop mode can be set for individual on-chip supporting modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the A/D converter are retained.
After reset clearance, all modules other than DMAC and flash memory are in module stop mode.
When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
When a transition is made to sleep mode with all modules stopped, the bus controller and I/O ports
also stop operating, enabling current dissipation to be further reduced.
Module Stop Mode
STBY
RES
NMI
Figure 20.7 Timing of Recovery from Hardware Standby Mode
t ≥100 ns
Rev.7.00 Dec. 24, 2008 Page 623 of 698
t
OSC
t
NMIRH
REJ09B0074-0700
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