HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 115

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8.1.3
Table 8.1 shows the BSC pin configuration.
Table 8.1
Name
Chip select 7–0
Read
High write
Low write
Write
High byte strobe
Low byte strobe
Row address strobe
High column
address strobe
Low column address
strobe
Address hold
Wait
Address bus
Data bus
Data bus parity high
Data bus parity low
Notes: 1. Doubles with the WRL pin. (Selected by the BAS bit of the BCR. See section 8.2.1, Bus
8.1.4
The BSC has ten registers (listed in table 8.2) which control space division, wait states, DRAM
interface, and parity check.
2. Doubles with the A0 pin. (Selected by the BAS bit of the BCR. See section 8.2.1, Bus
3. Doubles with the WRH pin. (Selected by the BAS bit of the BCR. See section 8.2.1, Bus
Pin Configuration
Register Configuration
Control Register, for details.
Control Register, for details.
Control Register, for details.
Pin Configuration
Abbreviation
CS7–CS0
RD
WRH
WRL
WR*
HBS*
LBS*
RAS
CASH
CASL
AH
WAIT
A21–A0
AD15–AD0
DPH
DPL
1
3
2
I/O Function
O
O
O
O
O
O
O
O
O
O
O
I
O
I/O Data I/O. During address/data multiplexing, address
I/O Parity data I/O for upper byte
I/O Parity data I/O for lower byte
Chip select signal that indicates the area being
accessed
Strobe signal that indicates the read cycle
Strobe signal that indicates write cycle to upper 8 bits
Strobe signal that indicates write cycle to lower 8 bits
Strobe signal that indicates write cycle
Strobe signal that indicates access to upper 8 bits
Strobe signal that indicates access to lower 8 bits
DRAM row address strobe signal
Column address strobe signal for accessing the
upper 8 bits of the DRAM
Column address strobe signal for accessing the lower
8 bits of the DRAM
Signal for holding the address for address/data
multiplexing
Wait state request signal
Address output
output and data input/output.
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