HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 257

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.2.11 Timer Status Register (TSR)
The timer status register (TSR) is an eight-bit read/write register containing flags that indicate
timer counter (TCNT) overflow/underflow and general register (GRA/GRB) compare match or
input capture. These flags are interrupt sources. If the interrupt is enabled by the corresponding bit
in the timer interrupt enable register (TIER), an interrupt is requested of the CPU. TSR is
initialized by a reset or standby mode to H'F8 or H'78. Each ITU channel has one TSR (table
10.9).
Table 10.9 Timer Status Register (TSR)
Channel
0
1
2
3
4
Notes: 1. Undefined
• Bits 7–3 (reserved): Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value
• Bit 2 (overflow flag (OVF)): OVF indicates a TCNT overflow/underflow has occurred.
Bit 2: OVF
0
1
Note: A TCNT underflow occurs when the TCNT up/down counter is functioning. It may occur in
to bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1.
Initial value:
the following cases: (1) When channel 2 is set in the phase counting mode (MDF bit of
TMDR is 1), or (2) When channel 3 and 4 are set to the complementary PWM mode (CMD1
bit of TFCR is 1 and CMD0 bit is 0).
2. Write 0 to clear the flag.
Bit name:
R/W:
Bit:
Abbreviation
TSR0
TSR1
TSR2
TSR3
TSR4
—
—
*
7
1
Description
Clearing condition: Read OVF when OVF = 1, then write 0 in OVF
(initial value)
Setting condition: TCNT overflowed from H'FFFF–H'0000 or
underflowed from H'0000–H'FFFF.
—
—
6
1
Function
The TSR indicates input capture, compare match and
overflow status.
—
—
5
1
—
—
4
1
—
—
3
1
R/(W)*
OVF
2
0
2
R/(W)*
IMFB
RENESAS 239
1
0
2
R/(W)*
IMFA
0
0
2