HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 40

SH 1 CORE 32B MPU, 20MHZ/5V, 100

HD6417020SX20IV

Manufacturer Part Number
HD6417020SX20IV
Description
SH 1 CORE 32B MPU, 20MHZ/5V, 100
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6417020SX20IV

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
2.1.4
Table 2.1 lists the values of the registers after reset.
Table 2.1
Classification
General register
Control register
System register
2.2
2.2.1
Register operands are always long words (32 bits). When the memory operand is only a byte (8
bits) or a word (16 bits), it is sign-extended into a long word when stored into a register (figure
2.4).
31
31
31
Initial Values of Registers
Data Formats
Data Format in Registers
(sign extended)
Initial Values of Registers
Register
R0–R14
R15 (SP)
SR
GBR
VBR
MACH, MACL, PR
PC
MACL
PR
PC
Figure 2.3 System Registers
9
MACH
Initial Value
Undefined
Value of the stack pointer in the vector address table
Bits I0-I3 are 1111(H'F), reserved bits are 0, and other
bits are undefined
Undefined
H'00000000
Undefined
Value of the program counter in the vector address
table
0
0
0
Multiply and accumulate (MAC) registers
high and low (MACH, MACL): Store the
results of multiply and accumulate opera-
tions. MACH is sign-extended when read
because only the lowest 10 bits are valid.
Procedure register (PR): Stores a return
address from a subroutine procedure.
Program counter (PC): Indicates the
fourth byte (second instruction) after
the current instruction.
RENESAS17

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