HD64F3644WV Renesas Electronics America, HD64F3644WV Datasheet - Page 45
HD64F3644WV
Manufacturer Part Number
HD64F3644WV
Description
IC H8/3644 MCU FLASH 80TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD64F3644HV.pdf
(551 pages)
Specifications of HD64F3644WV
Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3644WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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2.4
2.4.1
The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a
subset of these addressing modes.
Table 2.1
No.
1
2
3
4
5
6
7
8
1. Register Direct Rn: The register field of the instruction specifies an 8- or 16-bit general
2. Register Indirect @Rn: The register field of the instruction specifies a 16-bit general
3. Register Indirect with Displacement @(d:16, Rn): The instruction has a second word
4. Register Indirect with Post-Increment or Pre-Decrement @Rn+ or @–Rn:
register containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
register containing the address of the operand in memory.
(bytes 3 and 4) containing a displacement which is added to the contents of the specified
general register to obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting
address must be even.
Register indirect with post-increment @Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
The register field of the instruction specifies a 16-bit general register containing the address
of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B
or 2 for MOV.W, and the result of the addition is stored in the register. For MOV.W, the
original contents of the 16-bit general register must be even.
Addressing Modes
Addressing Modes
Address Modes
Register direct
Register indirect
Register indirect with displacement
Register indirect with post-increment
Register indirect with pre-decrement
Absolute address
Immediate
Program-counter relative
Memory indirect
Addressing Modes
Symbol
Rn
@Rn
@(d:16, Rn)
@Rn+
@–Rn
@aa:8 or @aa:16
#xx:8 or #xx:16
@(d:8, PC)
@@aa:8
Rev. 6.00 Sep 12, 2006 page 23 of 526
REJ09B0326-0600
Section 2 CPU
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