MCF5216CVM66J Freescale Semiconductor, MCF5216CVM66J Datasheet - Page 540

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MCF5216CVM66J

Manufacturer Part Number
MCF5216CVM66J
Description
IC MCU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet

Specifications of MCF5216CVM66J

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5216CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Queued Analog-to-Digital Converter (QADC)
28.2
28.3
This subsection describes the two modes of operation in which the QADC does not perform conversions
in a regular fashion:
28.3.1
The QDBG bit in the module configuration register (QADCMCR) governs behavior of the QADC when
the CPU enters background debug mode. When QDBG is clear, the QADC operates normally and is
unaffected by CPU background debug mode. See
(QADCMCR).
When QDBG is set and the CPU enters background debug mode, the QADC finishes any conversion in
progress and then freezes. This is QADC debug mode. Depending on when debug mode is entered, the
three possible queue freeze scenarios are:
28-2
Debug mode
Stop mode
When a queue is not executing, the QADC freezes immediately.
When a queue is executing, the QADC completes the current conversion and then freezes.
Block Diagram
Modes of Operation
Debug Mode
External
Triggers
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
MUX Address
Interface
Control
IPBUS
Digital
External
Figure 28-1. QADC Block Diagram
(18 with External MUXing)
Analog Input MUX
Command Words
8 Analog Channels
Signal Functions
64-Entry Queue
Conversion
and Digital
Section 28.6.1, “QADC Module Configuration Register
of 10-bit
(CCWs)
Reference
Inputs
Result Alignment
Analog-to-Digital
64-Entry Table
10-bit to 16-bit
Converter
of 10-bit
Results
10-bit
Analog Power
Inputs
Freescale Semiconductor

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