DF2372VFQ34V Renesas Electronics America, DF2372VFQ34V Datasheet - Page 436

• Manufacturer Part Number: DF2372VFQ34V
• Description: IC H8S/2372 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2372VFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 EXDMA Controller (EXDMAC)
Bit
6
5
4
Rev.7.00 Mar. 18, 2009 page 368 of 1136
REJ09B0109-0700
Bit Name
IRF
TCEIE
SDIR
Initial Value
0
0
0
R/W
R/(W) *
R/W
R/W
Description
Interrupt Request Flag
Flag indicating that an interrupt request has
occurred and transfer has ended.
0: No interrupt request
[Clearing conditions]
•
•
1: Interrupt request occurrence
[Setting conditions]
•
•
•
Transfer Counter End Interrupt Enable
Enables or disables transfer end interrupt
requests by the transfer counter. When
transfer ends according to the transfer counter
while this bit is set to 1, the IRF bit is set to 1,
indicating that an interrupt request has
occurred.
0: Transfer end interrupt requests by transfer
1: Transfer end interrupt requests by transfer
Single Address Direction
Specifies the data transfer direction in single
address mode. In dual address mode, the
specification by this bit is ignored.
0: Transfer direction: EDSAR → external
1: Transfer direction: External device with
counter are disabled
counter are enabled
device with DACK
DACK→ EDDAR
Writing 1 to the EDA bit
Writing 0 to IRF after reading IRF = 1
Transfer end interrupt request generated by
transfer counter
Source address repeat area overflow interrupt
request
Destination address repeat area overflow
interrupt request